Texas Instruments Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.6 GHz VCO (LVPECL LVCMOS Outputs) LMK04002BEV LMK04002BEVAL/NOPB 데이터 시트
제품 코드
LMK04002BEVAL/NOPB
November 2013
LMK040xx Evaluation Board User’s Guide
SNAU045A
21
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Typical Phase Noise Performance
The following table lists the test conditions used for the phase noise measurements for the crystal oscillator option:
Table 4 . LMK040XX test conditions, XTAL Oscillator Option
Parameter
Value
PLL1 Reference clock input
CLKin0*, single-ended, CLKin0 AC-coupled to GND
PLL1 Reference Clock frequency 122.88 MHz
PLL1 Phase detector frequency
1024 kHz
PLL1 Charge Pump Gain
100 uA
VCXO frequency
12.288 MHz, Ecliptek ECX-6465
PLL2 phase detector frequency
12.288 MHz
PLL2 Charge Pump Gain
3200 uA
PLL2 REF2X mode
disabled
NOTE: All jitter measurements are for a 100 Hz to 20 MHz integration bandwidth.
The following plot illustrates the phase noise measured at F
OUT
, CLKout0 (LVDS), CLKout1 (LVPECL), and CLKout2
(LVCMOS) using the XTAL oscillator option.
Figure 5. Typical Phase Noise Performance at F
out
, Fvco = 1474.56 MHz, Fcomp2 = 12.288 MHz. XTAL
Resonator option. Jitter metrics are for an integration bandwidth of 100 Hz to 20 MHz.
The phase noise and jitter performance at the clock outputs of the LMK040XX is strongly dependent on the
phase noise characteristics of the VCXO or crystal driving the OSCin port
.
The next sets of phase noise plots represent typical performance achieved using modular VCXO packages with
PLL1. The first set of plots contains the VCXO phase noise plots for the 100 MHz VCXO and the 61.44 MHz VCXO.
LMK04021 Phase Noise, VCXO Freq = 12.288 MHz
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
100
1000
10000
100000
1000000
10000000
100000000
Offset (Hz)
dB
c
Fout, 1475.56 MHz, Tj = 265 fs
LVDS Output, 122.88 MHz, Tj = 266 fs
LVPECL Output, 122.88 MHz, Tj = 273 fs
LVCMOS Output, 122.88 MHz, Tj = 256 fs