Texas Instruments Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.6 GHz VCO (LVPECL LVCMOS Outputs) LMK04002BEV LMK04002BEVAL/NOPB 데이터 시트
제품 코드
LMK04002BEVAL/NOPB
22 SNAU045A
LMK040xx Evaluation Board User’s Guide
November 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Figure 6. LMK040X1 Evaluation Board, typical VCXO Phase Noise, 100 MHz and 61.44 MHz VCXOs.
The following table lists the test conditions used for the phase noise measurements based upon the VCXO option,
100 MHz:
Table 5. LMK040XX test conditions, 100 MHz VCXO Option, LMK04021
Parameter
Value
PLL1 Reference clock input
CLKin0, single-ended, CLKin0* AC-coupled to GND
PLL1 Reference Clock frequency 100 MHz
PLL1 Phase detector frequency
1000 kHz
PLL1 Charge Pump Gain
100 uA
VCXO frequency
100 MHz, Crystek CVPD-920
PLL2 phase detector frequency
50 MHz
PLL2 REF2X mode
disabled
PLL2 Charge Pump Gain
3200 uA
The following plot illustrates the phase noise performance of the LMK040XX using the VCXO option. The VCXO
represented in these plots is a Crystek CVPD-920-100MHz LVPECL model.
represented in these plots is a Crystek CVPD-920-100MHz LVPECL model.
LMK040x1 Evaluation Board VCXO Phase Noise
-160
-150
-140
-130
-120
-110
-100
-90
-80
100
1000
10000
100000
1000000
10000000
100000000
Offset (Hz)
dB
c
61.44MHz VCXO
100MHz VCXO
100MHz VCXO