Texas Instruments Three Input, Thirteen Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VC L LMK04816BEVAL/NOPB 데이터 시트

PLL1_R_DLY 

R delay causes clock outputs to lag clock input 
when in a 0-delay mode.  Increasing the R delay 
value increases the output phase lag relative to the 
input. 

P

LL2

 

PLL2_WND_SIZE 

If the phase error between the PLL2 reference and 
feedback clock is less than specified time, then the 
PLL2 lock counter increments. 

PLL2_DLD_CNT 

The reference and feedback of PLL2 must be within 
the window of phase error as specified by 
PLL2_WND_SIZE for this many cycles before 
PLL2 digital lock detect is asserted. 

EN_PLL2_REF_2X 

Enables the doubler block to doubles the reference 
frequency into the PLL2 R counter.  This can allow 
for frequency of 2/3, 2/5, etc. of OSCin to be used 
at the phase detector of PLL2. 

PLL2_N_CAL 

The PLL2_N_CAL register contains the N value 
used for the VCO calibration routine.  Except 
during 0-delay modes, the PLL2_N and 
PLL2_N_CAL registers will be exactly the same. 

PLL2_R3_LF 

Set the corresponding integrated PLL2 loop filter 
values: R3, R4, C3, and C4. 
It is also possible to set these values by clicking on 
the loop filter values on the Clock Outputs tab. 

PLL2_R4_LF 
PLL2_C3_LF 
PLL2_C4_LF 
PLL2_FAST_PDF 

Enable this bit when using a PLL2 phase detector 
frequency > 100 MHz. 

Program Pins 

SYNC 

Sets these pins on the uWire header to logic high 
(checked) or logic low (unchecked). 

Status_CLKin0 
Status_CLKin1