Texas Instruments Three Input, Thirteen Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VC L LMK04816BEVAL/NOPB 데이터 시트
제품 코드
LMK04816BEVAL/NOPB
L M K 0 4 8 1 6 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU107
34
HOLDOVER_TYPE
Sets I/O pin type on the Status_Holdover pin.
Status_CLKin0 _MUX
Sets the selected signal on the Status_CLKin0 pin.
Status_CLKin0_TYPE
Sets I/O pin type on the Status_CLKin0 pin.
Status_CLKin1_MUX
Sets the selected signal on the Status_CLKin1 pin.
Status_CLKin1_TYPE
Sets I/O pin type on the Status_CLKin1 pin.
CLKin_Sel_INV
Inverts the Status_CLKin0/1 pin polarity when set
to an input type. Significant when
CLKin_SELECT_MODE is 3 or 6.
to an input type. Significant when
CLKin_SELECT_MODE is 3 or 6.
IO
C
ontrol
–
S
ync
SYNC_MUX
Sets the selected signal on the SYNC pin.
SYNC_TYPE
Sets I/O pin type on the SYNC pin.
SYNC_POL_INV
Sets polarity on SYNC input to active low when
checked. Toggling this bit will initiate a SYNC
event.
checked. Toggling this bit will initiate a SYNC
event.
SYNC_PLL1_DLD
Engage SYNC mode until PLL1 DLD is true
SYNC_PLL2_DLD
Engage SYNC mode until PLL2 DLD is true
NO_SYNC_CLKoutX_Y Synchronization will not affect selected clock
outputs, where X = even-numbered output and Y =
odd-numbered output.
odd-numbered output.
SYNC_QUAL
Sets the SYNC to qualify mode for dynamic digital
delay.
delay.
EN_SYNC
Must be set when using SYNC, but may be cleared
after the SYNC event. When using dynamic digital
delay (SYNC_QUAL = 1), EN_SYNC must always
be set.
Changing this value from 0 to 1 can cause a SYNC
event, so clocks which should not be SYNCed
when setting this bit should have the
NO_SYNC_CLKoutX_Y bit set.
NOTE: This bit is not a valid method of generating
a SYNC event. Use one of the other SYNC
generation methods to ensure a proper SYNC
occurs.
after the SYNC event. When using dynamic digital
delay (SYNC_QUAL = 1), EN_SYNC must always
be set.
Changing this value from 0 to 1 can cause a SYNC
event, so clocks which should not be SYNCed
when setting this bit should have the
NO_SYNC_CLKoutX_Y bit set.
NOTE: This bit is not a valid method of generating
a SYNC event. Use one of the other SYNC
generation methods to ensure a proper SYNC
occurs.
SYNC_EN_AUTO
Enable auto SYNC when R0 to R5 is written.
DA
C
/Holdover
HOLDOVER_MODE
Sets holdover mode to be disabled or enabled.
FORCE_HOLDOVER
Engages holdover when checked regardless of
HOLDOVER_MODE value. Turns the DAC on.
HOLDOVER_MODE value. Turns the DAC on.
EN_TRACK
Enables DAC tracking. DAC tracks the PLL1
Vtune to provide for an accurate HOLDOVER
mode. DAC_CLK_DIV should also be set so that
DAC update rate is <= 100 kHz.
Vtune to provide for an accurate HOLDOVER
mode. DAC_CLK_DIV should also be set so that
DAC update rate is <= 100 kHz.
EN_VTUNE_RAIL_DET Allows rail-to-rail operation of VCXO with default
of 0. Allows use of DAC_LOW_TRIP,
DAC_HIGH_TRIP. Must be used with
EN_MAC_DAC = 1. CLKin_SELECT_MODE
must be 4 or 6 (auto mode) to use.
DAC_HIGH_TRIP. Must be used with
EN_MAC_DAC = 1. CLKin_SELECT_MODE
must be 4 or 6 (auto mode) to use.