Texas Instruments LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input LMK00105BEVAL/NOP LMK00105BEVAL/NOPB 데이터 시트
제품 코드
LMK00105BEVAL/NOPB
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
13
14
15
16
2
4
2
3
2
2
2
1
2
0
1
9
18
17
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
Vddo
GND
Vddo
Vddo
GND
Vddo
GND
Vd
d
C
L
Ki
n
G
N
D
O
E
SEL
C
L
Ki
n
*
G
N
D
O
SC
in
G
N
D
G
N
D
Vd
d
O
SC
o
u
t
DAP
SNAS579F – MARCH 2012 – REVISED MAY 2013
Connection Diagram
24-Pin WQFN Package
PIN DESCRIPTIONS
Pin #
Pin Name
Type
Description
DAP
DAP
-
The DAP should be grounded
2, 6
Vddo
Power
Power Supply for Bank A (CLKout0 and CLKout 1) CLKout pins.
3
CLKout0
Output
LVCMOS Output
1,4,7,11,
GND
GND
Ground
12, 16,19
5
CLKout1
Output
LVCMOS Output
8,23
Vdd
Power
Supply for operating core and input buffer
9
OSCin
Input
Input for Crystal
10
OSCout
Output
Output for Crystal
13
CLKout2
Output
LVCMOS Output
14,18
Vddo
Power
Power Supply for Bank B (CLKout2 to CLKout 4) CLKout pins
15
CLKout3
Output
LVCMOS Output
17
CLKout4
Output
LVCMOS Output
20
CLKin*
Input
Complementary input pin
21
CLKin
Input
Input Pin
22
SEL
Input
Input Clock Selection. This pin has an internal pull-down resistor.
(1)
24
OE
Input
Output Enable. This pin has an internal pull-down resistor.
(1)
(1)
CMOS control input with internal pull-down resistor.
2
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