Texas Instruments LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input LMK00105BEVAL/NOP LMK00105BEVAL/NOPB 데이터 시트
제품 코드
LMK00105BEVAL/NOPB
SNAS579F – MARCH 2012 – REVISED MAY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Parameter
Symbol
Ratings
Units
Core Supply Voltage
Vdd
-0.3 to 3.6
V
Output Supply Voltage
Vddo
-0.3 to 3.6
V
Input Voltage
V
IN
-0.3 to Vdd + 0.3
V
Storage Temperature Range
T
STG
-65 to 150
°C
Lead Temperature (solder 4 s)
T
L
+260
°C
Junction Temperature
T
J
+125
°C
(1)
"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2)
This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD
protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.
protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Ambient Temperature
T
A
-40
25
85
°C
Core Supply Voltage
Vdd
2.375
3.3
3.45
V
Output Supply Voltage
(1)
Vddo
1.425
3.3
Vdd
V
(1)
V
ddo
should be less than or equal to V
dd
(V
ddo
≤
V
dd
)
Package Thermal Resistance
24-Lead WQFN
Package
Symbols
Ratings
Units
Thermal resistance from junction to ambient on 4-layer Jedec board
(1)
θ
JA
50.6
° C/W
Thermal resistance from junction to case
(2)
θ
JC (DAP)
20.1
° C/W
(1)
Specification assumes 4 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias
play a key role in improving the thermal performance of the WQFN. For best thermal dissipation it is recommended that the maximum
number of vias be used on the board layout.
play a key role in improving the thermal performance of the WQFN. For best thermal dissipation it is recommended that the maximum
number of vias be used on the board layout.
(2)
Case is defined as the DAP (die attach pad).
Copyright © 2012–2013, Texas Instruments Incorporated
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