Texas Instruments TPS59640EVM-751 Evaluation Module TPS59640EVM-751 TPS59640EVM-751 데이터 시트
제품 코드
TPS59640EVM-751
Configuration
6.1.9
IMVP-7 VR_ON Enable Selection (S4)
The IMVP-7 CPU/GPU can be enabled and disabled by S4.
Default setting: Push S4 to OFF position to disable both CPU and GPU.
Table 10. VR_ON Enable Selection
Switch Set to
VR_ON Selection
Push S4 to ON position
Enable IMVP-7 CPU/GPU Vcore
Push S4 to OFF position
Disable IMVP-7 CPU/GPU Vcore
6.2
1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration
6.2.1
VDDQ S3, S5 Enable Selection
The controller can be enabled and disabled by J26 and J27.
Default setting: Jumper shorts on Pin 2 and Pin 3 of J27,
Default setting:
Jumper shorts on Pin 2 and Pin 3 of J26
Table 11. VDDQ S3, S5 Enable Selection
State
J26 (S3) Set to
J27 (S5) Set to
VDDQ
VTTREF
VTT
S0
ON position
ON position
ON
ON
ON
S3
OFF position
ON position
ON
ON
OFF (High-Z)
S4/S5
OFF position
OFF position
OFF (Discharge)
OFF (Discharge)
OFF (Discharge)
6.3
1.05V VCCIO Configuration
6.3.1
1.05V Enable Selection (S1)
1.05V enable can be set by S1.
Default setting: Push S1 to OFF position
Default setting: Push S1 to OFF position
6.3.2
VCCIO Output Voltage Selection (J23)
The VCCIO output voltage can be selected by J23.
Default setting: Jumper shorts pin 1 and pin 2 of J23
Default setting: Jumper shorts pin 1 and pin 2 of J23
Table 12. VCCIO Output Voltage Selection
Jumper Set to
Selection
Jumper shorts on pin 1 and pin 2
VCCIO: 1.05 V
Jumper shorts on pin 2 and pin 3
VCCIO: 1.00 V
27
SLUU796
–
January 2012
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright
©
2012, Texas Instruments Incorporated