Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.2.2
Universal Asynchronous Receiver/Transmitter
This device has five UART modules. The CPU accesses data, control, and status information. The UART
also supports µDMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel
conversions. Each of the five UART modules is similar in functionality to a 16C550 UART, but is not
register-compatible.
also supports µDMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel
conversions. Each of the five UART modules is similar in functionality to a 16C550 UART, but is not
register-compatible.
The UART is configured for transmit and receive via the TXE bit and the RXE bit, respectively, of the
UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control
registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the
UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART
stopping.
UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control
registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the
UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART
stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an
infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the
UARTCTL register.
infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the
UARTCTL register.
shows the UART peripheral.
7.2.2.1
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The
number formed by these two values is used by the baud-rate generator to determine the bit period. Having
a fractional baud-rate divider allows the UART to generate all the standard baud rates.
number formed by these two values is used by the baud-rate generator to determine the bit period. Having
a fractional baud-rate divider allows the UART to generate all the standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6-
bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud
rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the
BRD, and BRDF is the fractional part, separated by a decimal place).
bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud
rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the
BRD, and BRDF is the fractional part, separated by a decimal place).
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in
UARTCTL is clear) or 8 (if HSE is set).
UARTCTL is clear) or 8 (if HSE is set).
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can
be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64,
and adding 0.5 to account for rounding errors:
be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64,
and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as
Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is
divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations.
Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is
divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD
registers form an internal 30-bit register. This internal register is only updated when a write operation to
UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the
UARTLCRH register for the changes to take effect.
registers form an internal 30-bit register. This internal register is only updated when a write operation to
UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the
UARTLCRH register for the changes to take effect.
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Peripheral Information and Timings
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