Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.2.5
Cortex-M3 Universal Serial Bus Controller
This device has one Cortex-M3 USB controller. The USB controller operates as a full-speed or low-speed
function controller during point-to-point communications with the USB Host, Device, or OTG functions. The
controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirty-
two endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and
one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support
multiple packet queuing. DMA access to the FIFO allows minimal interference from system software.
Software-controlled connect and disconnect allow flexibility during USB device start-up. The controller
complies with the OTG standard's Session Request Protocol (SRP) and Host Negotiation Protocol (HNP).
function controller during point-to-point communications with the USB Host, Device, or OTG functions. The
controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirty-
two endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and
one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support
multiple packet queuing. DMA access to the FIFO allows minimal interference from system software.
Software-controlled connect and disconnect allow flexibility during USB device start-up. The controller
complies with the OTG standard's Session Request Protocol (SRP) and Host Negotiation Protocol (HNP).
The USB controller includes the following features:
•
Complies with USB-IF certification standards
•
USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation
•
Integrated PHY
•
Four transfer types: Control, Interrupt, Bulk, and Isochronous
•
32 endpoints:
–
–
One dedicated control IN endpoint and one dedicated control OUT endpoint
–
15 configurable IN endpoints and 15 configurable OUT endpoints
•
4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
isochronous packet size
•
VBUS droop and valid ID detection and interrupt
•
Efficient transfers using DMA controller:
–
–
Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints
–
Channel requests asserted when FIFO contains required amount of data
•
Electrical specifications are compliant with the USB Specification Rev. 2.0 (full-speed and low-speed
support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of
the USB system are integrated within the Concerto microcontroller and are specific to its design.
support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of
the USB system are integrated within the Concerto microcontroller and are specific to its design.
shows the USB peripheral.
7.2.5.1
Functional Description
The USB controller provides full OTG negotiation by supporting both the SRP and the HNP. The SRP
allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used
after the initial session request protocol has powered the bus and provides a method to determine which
end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or
devices, the controller can detect which cable end was used and provides a register to indicate if the
controller should act as the Host controller or the Device controller. This indication and the mode of
operation are handled automatically by the USB controller. This autodetection allows the system to use a
single A/B connector instead of having both A and B connectors in the system, and supports full OTG
negotiations with other OTG devices.
allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used
after the initial session request protocol has powered the bus and provides a method to determine which
end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or
devices, the controller can detect which cable end was used and provides a register to indicate if the
controller should act as the Host controller or the Device controller. This indication and the mode of
operation are handled automatically by the USB controller. This autodetection allows the system to use a
single A/B connector instead of having both A and B connectors in the system, and supports full OTG
negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers.
The USB controller can be configured to act as either a dedicated Host or Device, in which case, the
USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a
self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt
when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal.
The USB controller can be configured to act as either a dedicated Host or Device, in which case, the
USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a
self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt
when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal.
NOTE
When the USB is used, the system clock frequency (SYSCLK) must be at least 20 MHz.
Copyright © 2012–2014, Texas Instruments Incorporated
Peripheral Information and Timings
203
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