Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
(A)
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
(minimum) before the valid SPI clock
edge and remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 7-44. SPI Slave Mode External Timing (Clock Phase = 0)
234
Peripheral Information and Timings
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