Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.3.7
C28x Multichannel Buffered Serial Port
This device provides one high-speed McBSP that allows direct interface to codecs and other devices. The
CPU accesses data, control, and status information. The MCBSP also supports µDMA transfers.
CPU accesses data, control, and status information. The MCBSP also supports µDMA transfers.
The McBSP consists of a data-flow path and a control path connected to external devices by six pins.
Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for
transmission and via the data receive (DR) pin for reception. Control information in the form of clocking
and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive
clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for
transmission and via the data receive (DR) pin for reception. Control information in the form of clocking
and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive
clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible
via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the
data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the transmit shift
registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers
(RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is
then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows
simultaneous movement of internal and external data communications.
via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the
data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the transmit shift
registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers
(RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is
then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows
simultaneous movement of internal and external data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is
8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant
bits.
8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant
bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and
FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads
instead of the CLKR and FSR pins.
FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads
instead of the CLKR and FSR pins.
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Peripheral Information and Timings
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