Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.3.7
Cortex-M3 Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem.
Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem.
The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and
eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity
Error Checking.
eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity
Error Checking.
The Message RAMs and the Shared RAMs can be accessed by the Cortex-M3 CPU and µDMA. The
MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem,
having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM
Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having
R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.
MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem,
having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM
Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having
R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the
Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays
associated with polling).
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the
Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays
associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;
however, the direction of the data flow can be individually set for each block to be from Master to Control
Subsystem or from Control to Master Subsystem.
however, the direction of the data flow can be individually set for each block to be from Master to Control
Subsystem or from Control to Master Subsystem.
The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed
through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and
DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the
C28x CPU only. The Cortex-M3 CPU accesses the ACIB through the System Bus, and the µDMA through
the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between
CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to
managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem
(as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources
from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations
in both the Master Subsystem and the Control Subsystem.
through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and
DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the
C28x CPU only. The Cortex-M3 CPU accesses the ACIB through the System Bus, and the µDMA through
the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between
CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to
managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem
(as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources
from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations
in both the Master Subsystem and the Control Subsystem.
See
for more information on shared resources and analog peripherals.
3.4
Control Subsystem
The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block,
DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared
Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals via the Analog
Common Interface Bus.
DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared
Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals via the Analog
Common Interface Bus.
shows the Control Subsystem.
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