Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
Table 3-17. PIE Peripheral Interrupts
(1)
PIE INTERRUPTS
CPU INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
C28.LPMWAKE
TINT0
Reserved
XINT2
XINT1
Reserved
ADCINT2
ADCINT1
INT1
(C28LPM)
(TIMER 0)
–
–
–
–
(ADC)
(ADC)
0x0D4E
0x0D4C
0x0D4A
0x0D48
0x0D46
0x0D44
0x0D42
0x0D40
EPWM8_TZINT
EPWM7_TZINT
EPWM6_TZINT
EPWM5_TZINT
EPWM4_TZINT
EPWM3_TZINT
EPWM2_TZINT
EPWM1_TZINT
INT2
(ePWM8)
(ePWM7)
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
0x0D5E
0x0D5C
0x0D5A
0x0D58
0x0D56
0x0D54
0x0D52
0x0D50
EPWM8_INT
EPWM7_INT
EPWM6_INT
EPWM5_INT
EPWM4_INT
EPWM3_INT
EPWM2_INT
EPWM1_INT
INT3
(ePWM8)
(ePWM7)
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
0x0D6E
0x0D6C
0x0D6A
0x0D68
0x0D66
0x0D64
0x0D62
0x0D60
EPWM9_TZINT
EPWM10_TZINT
ECAP6_INT
ECAP5_INT
ECAP4_INT
ECAP3_INT
ECAP2_INT
ECAP1_INT
INT4
(ePWM9)
(ePWM10)
(eCAP6)
(eCAP5)
(eCAP4)
(eCAP3)
(eCAP2)
(eCAP1)
0x0D7E
0x0D7C
0x0D7A
0x0D78
0x0D76
0x0D74
0x0D72
0x0D70
EPWM9_INT
EPWM10_INT
Reserved
Reserved
Reserved
EQEP3_INT
EQEP2_INT
EQEP1_INT
INT5
(ePWM9)
(ePWM10)
–
–
–
(eQEP3)
(eQEP2)
(eQEP1)
0x0D8E
0x0D8C
0x0D8A
0x0D88
0x0D86
0x0D84
0x0D82
0x0D80
EPWM11_TZINT
EPWM12_TZINT
MXINTA
MRINTA
Reserved
Reserved
SPITXINTA
SPIRXINTA
INT6
(ePWM11)
(ePWM12)
(McBSPA)
(McBSPA)
–
–
(SPIA)
(SPIA)
0x0D9E
0x0D9C
0x0D9A
0x0D98
0x0D96
0x0D94
0x0D92
0x0D90
EPWM11_INT
EPWM12_INT
DINTCH6
DINTCH5
DINTCH4
DINTCH3
DINTCH2
DINTCH1
INT7
(ePWM11)
(ePWM12)
(C28 DMA)
(C28 DMA)
(C28 DMA)
(C28 DMA)
(C28 DMA)
(C28 DMA)
0x0DAE
0x0DAC
0x0DAA
0x0DA8
0x0DA6
0x0DA4
0x0DA2
0x0DA0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
I2CINT1A
INT8
–
–
–
–
–
–
(I2CA)
(I2CA)
0x0DBE
0x0DBC
0x0DBA
0x0DB8
0x0DB6
0x0DB4
0x0DB2
0x0DB0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCITXINTA
SCIRXINTA
INT9
–
–
–
–
–
–
(SCIA)
(SCIA)
0x0DCE
0x0DCC
0x0DCA
0x0DC8
0x0DC6
0x0DC4
0x0DC2
0x0DC0
ADCINT8
ADCINT7
ADCINT6
ADCINT5
ADCINT4
ADCINT3
ADCINT2
ADCINT1
INT10
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
0x0DDE
0x0DDC
0x0DDA
0x0DD8
0x0DD6
0x0DD4
0x0DD2
0x0DD0
Reserved
Reserved
Reserved
Reserved
MTOCIPCINT4
MTOCIPCINT3
MTOCIPCINT2
MTOCIPCINT1
INT11
–
–
–
–
(IPC)
(IPC)
(IPC)
(IPC)
0x0DEE
0x0DEC
0x0DEA
0x0DE8
0x0DE6
0x0DE4
0x0DE2
0x0DE0
LUF
LVF
EPI_INT
C28RAMACCVIOL C28RAMSINGERR
Reserved
C28FLSINGERR
XINT3
INT12
(C28FPU)
(C28FPU)
(EPI)
(Memory)
(Memory)
–
(Memory)
(Ext. Int. 3)
0x0DFE
0x0DFC
0x0DFA
0x0DF8
0x0DF6
0x0DF4
0x0DF2
0x0DF0
(1)
Out of the 96 possible interrupts, 72 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
3.4.4
C28x Direct Memory Access
The C28x DMA module provides a hardware method of transferring data between peripherals, between
memory, and between peripherals and memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange
the data as the data is transferred as well as “ping-pong” data between buffers. These features are useful
for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six
DMA channels can be configured separately and each channel contains its own independent PIE interrupt
to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are
exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher
priority than the others.
memory, and between peripherals and memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange
the data as the data is transferred as well as “ping-pong” data between buffers. These features are useful
for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six
DMA channels can be configured separately and each channel contains its own independent PIE interrupt
to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are
exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher
priority than the others.
30
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