Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 데이터 시트
제품 코드
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.3
Master Subsystem
The Master Subsystem includes the Cortex-M3 CPU, µDMA, Nested Vectored Interrupt Controller (NVIC),
Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and µDMA can access the
Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and
read ADC Result Registers via the Analog Common Interface Bus. The Master Subsystem can also
receive events from the NMI block and send events to the Resets block.
Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and µDMA can access the
Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and
read ADC Result Registers via the Analog Common Interface Bus. The Master Subsystem can also
receive events from the NMI block and send events to the Resets block.
shows the Master Subsystem.
3.3.1
Cortex-M3 CPU
The 32-bit Cortex-M3 processor offers high performance, fast interrupt handling, and access to a variety of
communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection
Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge
adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that
connect to the Boot ROM and Flash. Other data is typically routed through the Cortex-M3 System Bus
connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible
by the Control Subsystem) and to the Analog Subsystem through the ACIB. Another bus bridge allows bus
cycles from both the Cortex-M3 System Bus and those of the µDMA bus to access the Master Subsystem
peripherals (via the APB bus or the AHP bus).
communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection
Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge
adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that
connect to the Boot ROM and Flash. Other data is typically routed through the Cortex-M3 System Bus
connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible
by the Control Subsystem) and to the Analog Subsystem through the ACIB. Another bus bridge allows bus
cycles from both the Cortex-M3 System Bus and those of the µDMA bus to access the Master Subsystem
peripherals (via the APB bus or the AHP bus).
Most of the interrupts to the Cortex-M3 CPU come from the NVIC, which manages the interrupt requests
from peripherals and assigns handling priorities. There are also several exceptions generated by Cortex-
M3 CPU that can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the
NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts
of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets
block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI
block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by
one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard
Fault because they are not enabled or not properly serviced.
from peripherals and assigns handling priorities. There are also several exceptions generated by Cortex-
M3 CPU that can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the
NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts
of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets
block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI
block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by
one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard
Fault because they are not enabled or not properly serviced.
The Cortex-M3 CPU has two low-power modes: Sleep and Deep Sleep.
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Device Overview
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