Texas Instruments THS7347EVM Evaluation Module THS7347EVM THS7347EVM 데이터 시트
제품 코드
THS7347EVM
Start
Condition
Clock Pulse for
Acknowledgement
Acknowledge
Not Acknowledge
Data Output
by Receiver
by Receiver
Data Output
by Transmitter
SCL From
Master
S
1
2
8
9
SCL
SDA
MSB
Slave Address
Data
Stop
1
2
3
4
5
6
7
8
9
9
1
2
3
4
5
6
7
8
9
Acknowledge
Acknowledge
SLOS531B
–
MAY 2007
–
REVISED OCTOBER 2011
Figure 7. I
2
C Acknowledge
•
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see
the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see
Figure 8. I
2
C Address and Data Cycles
•
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see
to high while the SCL line is high (see
). This transaction releases the bus and stops the
communication link with the addressed slave. All I
2
C-compatible devices must recognize the stop condition.
Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start
condition followed by a matching address.
condition followed by a matching address.
Copyright
©
2007
–
2011, Texas Instruments Incorporated
17