Texas Instruments LM49370RLEVAL Evaluation Board LM49370RLEVAL/NOPB LM49370RLEVAL/NOPB 데이터 시트
제품 코드
LM49370RLEVAL/NOPB
SDA
SCL
1
8
2
3
7
6
5
8
10
4
9
1
7
ack from slave
ack from slave
w
rs
r
stop
ack from slave
ack from master
repeated start
data from slave
start
w ack
ack
rs
r ack
ack stop
start
SCL
SDA
MSB Chip Address LSB
slave address =
0011010
2
register address = 0x00h
MSB Register 0x00h LSB
MSB Data LSB
MSB Chip Address LSB
slave address =
0011010
2
register 0x00h data
ack
ack
ack
ack
start
MSB Chip Address LSB
w
ack
MSB Register 0x02h LSB
ack
MSB Data LSB
ack
stop
ack from slave
ack from slave
ack from slave
SCL
SDA
start
slave address =
0011010
2
w
ack
register address = 0x02h
ack
ack
register 0x02h data
stop
SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012
Register changes take an effect at the SCL rising edge during the last ACK from slave.
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
Figure 6. Example I
2
C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
the Read Cycle waveform.
Figure 7. Example I
2
C Read Cycle
Figure 8. I
2
C Timing Diagram
I
2
C TIMING PARAMETERS
Symbol
Parameter
(1)
Limit
Units
Min
Max
1
Hold Time (repeated)
0.6
µs
START Condition
2
Clock Low Time
1.3
µs
3
Clock High Time
600
ns
4
Setup Time for a
600
ns
Repeated START
Condition
Condition
(1)
Data specified by design
Copyright © 2007–2012, Texas Instruments Incorporated
13
Product Folder Links: