Texas Instruments LM49370RLEVAL Evaluation Board LM49370RLEVAL/NOPB LM49370RLEVAL/NOPB 데이터 시트
제품 코드
LM49370RLEVAL/NOPB
CLK
SDI
T
SPISETENB
T
SPIHOLDD
T
SPISETD
T
SPICH
T
SPIT
T
SPICL
T
SPIHOLDENB
TEST_MODE/CS
SDI
15
14
CLK
Ignored
8
Register Address
GPIO2
4
1
11
TEST_MODE/CS
Register Data
SDI
15
14
0
1
CLK
7
8
Register Address
Write Data
TEST_MODE/CS
SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012
5
Data Hold Time (Output
300
900
ns
direction, delay generated
by LM49370)
by LM49370)
5
Data Hold Time (Input
0
900
ns
direction, delay generated
by the Master)
by the Master)
6
Data Setup Time
100
ns
7
Rise Time of SDA and
20+0.1C
b
300
ns
SCL
8
Fall Time of SDA and SCL
15+0.1C
b
300
ns
9
Set-up Time for STOP
600
ns
condition
10
Bus Free Time between a
1.3
µs
STOP and a START
Condition
Condition
C
b
Capacitive Load for Each
10
200
pF
Bus Line
Method 2. SPI/Microwire Control/3–wire Control
The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low
chip_select. To use this control method connect SPI_MODE to BB_V
chip_select. To use this control method connect SPI_MODE to BB_V
DD
and use TEST_MODE/CS as the
chip_select as follows:
Figure 9. SPI Write Transaction
If the application requires read access to the register set; for example to determine the cause of an interrupt
request, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the
GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address
the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-
only locations above 0x80h:
request, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the
GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address
the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-
only locations above 0x80h:
Figure 10. SPI Read Transaction
Figure 11. Three Wire Mode Write Bus Timing
Figure 12. SPI Timing
14
Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Links: