Texas Instruments CDCM6208V2 Evaluation Module CDCM6208V2EVM CDCM6208V2EVM 데이터 시트
제품 코드
CDCM6208V2EVM
Configuring the Board
Status Pin (STATUS1/PIN0): Depending on the operation mode, this is either an input or output pin. In
Interface-programming mode, this pin (header STATUS1_PIN0) provides the indication of a particular
reference clock selection to the PLL or PLL lock and/or unlock or loss of references depending on
Register 3 Bit 10-12 settings. See
Interface-programming mode, this pin (header STATUS1_PIN0) provides the indication of a particular
reference clock selection to the PLL or PLL lock and/or unlock or loss of references depending on
Register 3 Bit 10-12 settings. See
for a full description:
Table 3. STATUS1 Functional Description
Status Signal
Signal Type
Register Bit
Description
Name
SEL_REF
LVCMOS
R3.12
Indicates reference selected for PLL:
“0”
“0”
→
Primary
“1”
→
Secondary
LOSS_REF
LVCMOS
R3.11
Loss of reference input observed at input, Smart MUX output in observation
window for PLL:
“0”
window for PLL:
“0”
→
Reference input present
“1”
→
Loss of reference inputs
PLL_UNLOCK
LVCMOS
R3.10
Indicates unlock status for PLL:
“0”
“0”
→
PLL locked
“1”
→
PLL unlocked
In pin mode, this becomes an input pin and the header pin, STATUS1_PIN0, is controlled by PIN0 which
connects to GND or DVDD.
connects to GND or DVDD.
Device Control Pins (SDI/SDA/PIN1, SDO/AD0/PIN2, SCS/AD1/PIN3 and SCL/PIN4): These four pins
have multiple functions depending on the device’s programming interface (SPI or I
have multiple functions depending on the device’s programming interface (SPI or I
2
C) and pin-control
modes. See the data sheet (
) for detailed descriptions and see
for jumper
connections.
Table 4. Device Control Pin Functions
Programming
Header
Header
Header
Header
Remarks
Mode
SDI_SDA_PIN1
SDO_AD0_PIN2
SCS_ADI_PIN3
SCL_PIN4
SPI
Open
Open
Open
Open
Jumpers must not be connected in this mode
Open
GND
(1)
GND
(1)
Open
Header SDO_ADO_PIN2 and SCS_ADI_PIN3
I
2
C
provide the I
2
C address option
Pin Mode
DVDD or GND
DVDD or GND
DVDD or GND
DVDD or GND
The pin selections determine the predefined device’s
functional condition
functional condition
(1)
The control software assumes the default address bit settings for AD[1:0] is 00.
7.5
Selecting the Loop Filter
The CDCM6208 includes an on-chip PLL with a partially-integrated loop filter. External loop components
(C1, C2 and R2) are required to complete the PLL. The external loop filter is chosen by selecting one from
the four available options on the CDCM6208EVM using the dip switch, SW5. Depending upon the device’s
operation mode, synthesizer or jitter cleaning, selecting appropriate loop filter values is critical. Two loop
filters, 1 and 2, are for synthesizer mode and the other two filters, 3 and 4, are for jitter cleaning mode. If
different RC components are required based on the customer’s PLL configuration, these components
must be replaced by appropriate resistor and capacitors.
(C1, C2 and R2) are required to complete the PLL. The external loop filter is chosen by selecting one from
the four available options on the CDCM6208EVM using the dip switch, SW5. Depending upon the device’s
operation mode, synthesizer or jitter cleaning, selecting appropriate loop filter values is critical. Two loop
filters, 1 and 2, are for synthesizer mode and the other two filters, 3 and 4, are for jitter cleaning mode. If
different RC components are required based on the customer’s PLL configuration, these components
must be replaced by appropriate resistor and capacitors.
7.6
Configuring the Outputs
All eight outputs are connected to SMA through AC-coupling. Output Y4-Y7 can provide HCSL clocks.
These outputs have 50
These outputs have 50
Ω
-to-GND (not populated) and series-resistors (0-
Ω
populated) options. Placing
50-
Ω
resistors and possibly adjusting the series resistor values (up to 33
Ω
) improves ringing if the outputs
are configured as HCSL.
7.7
Using the MSP430 as a Bootloader
The onboard MSP430G2001 is a bootloader for the CDCM6208. A separate application note describes
how to generate, debug, and load the needed software for the MSP430.
how to generate, debug, and load the needed software for the MSP430.
10
CDCM6208 Evaluation Board
SCAU049A – May 2012 – Revised January 2013
Copyright © 2012–2013, Texas Instruments Incorporated