Texas Instruments AM18x eXperimenter's Kit TMDSEXP1808L TMDSEXP1808L 데이터 시트
제품 코드
TMDSEXP1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
7.5
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.6
Glossary
— TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
8
Mechanical Packaging and Orderable Information
This section describes the device orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
mechanical parameters.
8.1
Thermal Data for ZCE Package
The following table(s) show the thermal resistance characteristics for the PBGA–ZCE mechanical
package.
package.
Table 8-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]
NO.
°C/W
(1)
AIR FLOW (m/s)
(2)
1
R
Θ
JC
Junction-to-case
7.6
N/A
2
R
Θ
JB
Junction-to-board
11.3
N /A
3
R
Θ
JA
Junction-to-free air
23.9
0.00
4
21.2
0.50
5
20.3
1.00
R
Θ
JMA
Junction-to-moving air
6
19.5
2.00
7
18.6
4.00
8
0.2
0.00
9
0.3
0.50
10
Psi
JT
Junction-to-package top
0.3
1.00
11
0.4
2.00
12
0.5
4.00
13
11.2
0.00
14
11.1
0.50
15
Psi
JB
Junction-to-board
11.1
1.00
16
11.0
2.00
17
10.9
4.00
(1)
These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 500 mW and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness
and 1.5oz (50um) inner copper thickness
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 500 mW and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness
and 1.5oz (50um) inner copper thickness
(2)
m/s = meters per second
258
Mechanical Packaging and Orderable Information
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