Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 21: AES Control (AES_CTRL), offset 0x050
This register determines the mode of operation of the AES Engine.
AES Control (AES_CTRL)
Base 0x4403.6000
Offset 0x050
Type RW, reset 0x8000.0000
Offset 0x050
Type RW, reset 0x8000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GCM
CCM
CCM_L
CCM_M
reserved
SA
VE_CONTEXT
SVCTXTRDY
CTXTRDY
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
RW
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUTPUT_READY
INPUT_READY
DIRECTION
KEY_SIZE
MODE
CTR
CTR_WIDTH
ICM
CFB
XTS
F8
F9
CBCMAC
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Context Data Registers Ready
Description
Value
The context data registers are not ready to be overwritten.
0
The context data registers can be overwritten and the host is
permitted to write the next context.
permitted to write the next context.
1
1
RO
CTXTRDY
31
AES TAG/IV Block(s) Ready
Note:
This bit is only asserted if the
SAVE_CONTEXT
bit is set to 1.
This bit is mutual exclusive with the
CTXTRDY
bit.
Description
Value
AES authentication TAG and/or IV block(s) is/are not available.
0
Indicates the AES authentication TAG and /or IV block(s) is/are
available for the host to retrieve.
available for the host to retrieve.
1
0
RO
SVCTXTRDY
30
TAG or Result IV Save
If this bit is set, the
CONTEXT_OUT
interrupt bit is set in the
AES_IRQSTATUS register if the operation is finished and related signals
are enabled.
are enabled.
Description
Value
No effect.
0
Indicates an authentication TAG of result IV needs to be stored
as a result context.
as a result context.
1
0
RW
SAVE_CONTEXT
29
1013
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller