Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Table 15-4. Inner Digest Registers
HMAC Key
Processing (write)
SHA-256
(Read/Write)
SHA-2
(Read/Write)
SHA-1
(Read/Write)
MD5
(Read/Write)
Address
Register
HMAC key
[287:256]
Inner digest
[255:224]
Inner digest
[223:192]
Inner digest
[159:128]
Inner digest
[127:96]
0x020
SHA_IDIGEST_A
HMAC key
[319:288]
Inner digest
[223:192]
Inner digest
[191:160]
Inner digest
[127:96]
Inner digest
[95:64]
0x024
SHA_IDIGEST_B
HMAC key
[351:320]
Inner digest
[191:160]
Inner digest
[159:128]
Inner digest
[95:64]
Inner digest
[63:32]
0x028
SHA_IDIGEST_C
HMAC key
[383:352]
Inner digest
[159:128]
Inner digest
[127:96]
Inner digest
[63:32]
Inner digest
[31:0]
0x02C
SHA_IDIGEST_D
HMAC key
[415:384]
Inner digest
[127:96]
Inner digest
[95:64]
Inner
digest[31:0]
0x030
SHA_IDIGEST_E
HMAC key
[447:416]
Inner digest [95:64]
Inner digest
[63:32]
0x034
SHA_IDIGEST_F
HMAC key
[479:448]
Inner digest [63:32]
Inner digest [31:0]
0x038
SHA_IDIGEST_G
HMAC key
[511:480]
Inner digest[31:0]
0x03C
SHA_IDIGEST_H
Note:
Inner digests are initial, intermediate, and result digests.
Outer Digest Registers
The SHA_ODIGEST_A to SHA_ODIGEST_H registers are relevant only for HMAC operations; the
contents are ignored for hash operations.
contents are ignored for hash operations.
Before writing to the digest registers, the operation must be configured in the SHA Mode
(SHA_MODE) register. For HMAC operations without key processing, the
(SHA_MODE) register. For HMAC operations without key processing, the
HMAC_KEY_PROC
bit
must be clear in the SHA_MODE register before starting operations. Once the algorithm has been
programmed in the SHA_MODE register, only the relevant digest registers for the selected algorithm
must be written:
programmed in the SHA_MODE register, only the relevant digest registers for the selected algorithm
must be written:
■ SHA_ODIGEST_A to SHA_ODIGEST_D registers for MD5
■ SHA_ODIGEST_A to SHA_ODIGEST_E registers for SHA-1
■ SHA_ODIGEST_A to SHA_ODIGEST_H registers for SHA-2 (224 to 256)
When HMAC key processing is enabled (
HMAC_KEY_PROC
=1), these registers must be written with
the lower 256 bits of the HMAC key to be processed in little-endian format (first byte of key string
in bits [7:0]).
in bits [7:0]).
Note:
If the HMAC key is less than 512 bits, it must be properly padded with zeros: all 16 HMAC
key registers must be written explicitly; the core does not pad. Additionally, if the HMAC
key is larger than 512 bits, the host must perform a preprocessing step to reduce it to one
512-bit block. This involves hashing the large key and padding the hash result with zeros
until it is 512 bits wide.
key registers must be written explicitly; the core does not pad. Additionally, if the HMAC
key is larger than 512 bits, the host must perform a preprocessing step to reduce it to one
512-bit block. This involves hashing the large key and padding the hash result with zeros
until it is 512 bits wide.
The computed outer digest can be read from these registers when the SHA Interrupt Status
(SHA_IRQSTATUS) register when the
(SHA_IRQSTATUS) register when the
OUTPUT_READY
bit has been set indicating that the operation
is done.
Note:
If no HMAC key processing is performed, the value read is identical to the value written
initially. The MD5 outer digest is available from registers SHA_ODIGEST_A to
initially. The MD5 outer digest is available from registers SHA_ODIGEST_A to
December 13, 2013
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Texas Instruments-Advance Information
SHA/MD5 Accelerator