Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Table 15-7. SHA/MD5 Performance (continued)
Cycles per block
Cycles per operation
Algorithm
Operation
65
196 / 261
MD5
HMAC from Key
81
244 / 325
SHA-1
65
196 / 261
SHA-224
65
196 / 261
SHA-256
65
66 / 131
MD5
81
82 / 163
SHA-1
HMAC from
precomputes
precomputes
65
66 / 131
SHA-224
65
66 / 131
SHA-256
Note:
An extra block needs to be processed if the length of the data block to be hashed module
64 is 0 or equal to 56.
64 is 0 or equal to 56.
15.1.7
SHA/MD5 Programming Guide
This section covers the hardware programming sequences for configuration and use of the SHA/MD5
Module.
Module.
15.1.7.1
Global Initialization
Surrounding Modules Global Initialization
This section identifies the requirements for initializing the surrounding modules when the SHAM is
used for the first time after a device reset.
used for the first time after a device reset.
1.
When reset has completed, enable the SHA/MD5 Module by setting the
R0
bit in the CRC And
Cryptographic Modules Run Mode Clock Gating Control (RCGCCCM) register, System
Control offset 0x674. When the
Control offset 0x674. When the
R0
bit is set in the CRC and Cryptographic Modules (PRCCM)
register, System Control offset 0xA74 register, the SHA/MD5 Module is powered and ready to
be configured.
be configured.
2.
Configure the SHA µDMA channels for Context In, Context Out, Data In, and/or Data Out by
programming the appropriate encoding value in the DMA Channel Map Select n (DMACHMAPn)
register in the µDMA module, offset 0x510. For more information on how to program channel
assignments as well as enabling burst and the configured channels, refer to “Micro Direct
Memory Access (μDMA)” on page 707.
programming the appropriate encoding value in the DMA Channel Map Select n (DMACHMAPn)
register in the µDMA module, offset 0x510. For more information on how to program channel
assignments as well as enabling burst and the configured channels, refer to “Micro Direct
Memory Access (μDMA)” on page 707.
3.
Execute a software reset by setting the
SOFTRESET
bit in the SHA_SYSCONFIG register. When
reset is complete, the
RESETDONE
bit reads as 1 in the SHA_SYSSTATUS register.
4.
If the SHA channels are configured in the µDMA, enable the required SHA DMA requests by
programming bits [9:5] of the SHA_SYSCONFIG register, in addition to the completion interrupts
in the SHA DMA Interrupt Mask (SHA_DMAIM) register, CRC and Cryptographic Modules
offset 0x020.
programming bits [9:5] of the SHA_SYSCONFIG register, in addition to the completion interrupts
in the SHA DMA Interrupt Mask (SHA_DMAIM) register, CRC and Cryptographic Modules
offset 0x020.
Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
The following procedure is used to begin a new HMAC operation, starting from initial digest values.
1.
Load the key value in the SHA_ODIGEST_A/SHA_IDIGEST_A to
SHA_ODIGEST_H/SHA_IDIGEST_H registers.
SHA_ODIGEST_H/SHA_IDIGEST_H registers.
1077
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller