Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 44: SHA DMA Interrupt Clear (SHA_DMAIC), offset 0x01C
The SHA DMA Interrupt Clear register is used to clear the SHA_DMA_RIS and SHA_DMA_MIS
registers by writing a 1 to each register bit.
registers by writing a 1 to each register bit.
Note:
This registers always reads as zero.
SHA DMA Interrupt Clear (SHA_DMAIC)
Base
Offset 0x01C
Type W1C, reset 0x0000.0000
Offset 0x01C
Type W1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CIN
DIN
COUT
reserved
W1C
W1C
W1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:3
Context Out DMA Done Masked Interrupt Status
Writing a 1 to this bit clears the
COUT
bit in the SHA_DMA_RIS and
SHA_DMA_MIS register.
0
W1C
COUT
2
Data In DMA Done Interrupt Clear
Writing a 1 to this bit clears the
DIN
bit in the SHA_DMA_RIS and
SHA_DMA_MIS register.
0
W1C
DIN
1
Context In DMA Done Raw Interrupt Status
Writing a 1 to this bit clears the
CIN
bit in the SHA_DMA_RIS and
SHA_DMA_MIS register..
0
W1C
CIN
0
1101
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller