Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
GPTM Timer B Match Raw Interrupt
Description
Value
The match value has not been reached.
0
The
TBMIE
bit is set in the GPTMTBMR register, and the match
values in the GPTMTBMATCHR and (optionally) GPTMTBPMR
registers have been reached when configured in one-shot or
periodic mode.
registers have been reached when configured in one-shot or
periodic mode.
1
This bit is cleared by writing a 1 to the
TBMCINT
bit in the GPTMICR
register.
0
RO
TBMRIS
11
GPTM Timer B Capture Mode Event Raw Interrupt
Description
Value
The capture mode event for Timer B has not occurred.
0
A capture mode event has occurred for Timer B. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode.
asserts when the subtimer is configured in Input Edge-Time
mode.
1
This bit is cleared by writing a 1 to the
CBECINT
bit in the GPTMICR
register.
0
RO
CBERIS
10
GPTM Timer B Capture Mode Match Raw Interrupt
Description
Value
The capture mode match for Timer B has not occurred.
0
The capture mode match has occurred for Timer B. This interrupt
asserts when the values in the GPTMTBR and GPTMTBPR
match the values in the GPTMTBMATCHR and GPTMTBPMR
when configured in Input Edge-Time mode.
asserts when the values in the GPTMTBR and GPTMTBPR
match the values in the GPTMTBMATCHR and GPTMTBPMR
when configured in Input Edge-Time mode.
1
This bit is cleared by writing a 1 to the
CBMCINT
bit in the GPTMICR
register.
0
RO
CBMRIS
9
GPTM Timer B Time-Out Raw Interrupt
Description
Value
Timer B has not timed out.
0
Timer B has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTBILR, depending on the count
direction).
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTBILR, depending on the count
direction).
1
This bit is cleared by writing a 1 to the
TBTOCINT
bit in the GPTMICR
register.
0
RO
TBTORIS
8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
7:6
GPTM Timer A DMA Done Raw Interrupt Status
Description
Value
The Timer A DMA transfer has not completed.
0
The Timer A DMA transfer has completed.
1
0
RO
DMAARIS
5
December 13, 2013
1144
Texas Instruments-Advance Information
General-Purpose Timers