Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070
This register allows software to enable/disable GPTM ADC trigger events. Setting a bit enables the
corresponding ADC trigger, while clearing a bit disables it.
corresponding ADC trigger, while clearing a bit disables it.
GPTM ADC Event (GPTMADCEV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x070
Type RW, reset 0x0000.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x070
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TATOADCEN
CAMADCEN
CAEADCEN
RTCADCEN
TAMADCEN
reserved
TBTOADCEN
CBMADCEN
CBEADCEN
TBMADCEN
reserved
RW
RW
RW
RW
RW
RO
RO
RO
RW
RW
RW
RW
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:12
GPTM B Mode Match Event ADC Trigger Enable
When this bit is enabled, a a trigger pulse is sent to the ADC when a
mode match has occurred.
mode match has occurred.
Description
Value
Timer B Mode Match ADC trigger is disabled.
0
Timer B Mode Match ADC trigger is enabled.
1
0
RW
TBMADCEN
11
GPTM B Capture Event ADC Trigger Enable
When this bit is enabled, a trigger pulse is sent to the ADC when a
capture event has occurred.
capture event has occurred.
Description
Value
Timer B Capture Event ADC trigger is disabled.
0
Timer B Capture Event ADC trigger is enabled.
1
0
RW
CBEADCEN
10
GPTM B Capture Match Event ADC Trigger Enable
When this bit is enabled, a trigger signal is sent to the ADC when a
capture match event has occurred.
capture match event has occurred.
Description
Value
Timer B Capture Match ADC trigger is disabled.
0
Timer B Capture Match ADC trigger is enabled.
1
0
RW
CBMADCEN
9
1169
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller