Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 28: GPTM Clock Configuration (GPTMCC), offset 0xFC8
The GPTMCC register controls the clock source for the General-Purpose Timer module.
Note:
When the
ALTCLK
bit is set in the GPTMCC register to enable using the alternate clock
source, the synchronization imposes restrictions on the starting count value (down-count),
terminal value (up-count) and the match value. This restriction applies to all modes of
operation. Each event must be spaced by 4 Timer (ALTCLK) clock periods + 2 system clock
periods. If some events do not meet this requirement, then it is possible that the timer block
may need to be reset for correct functionality to be restored.
terminal value (up-count) and the match value. This restriction applies to all modes of
operation. Each event must be spaced by 4 Timer (ALTCLK) clock periods + 2 system clock
periods. If some events do not meet this requirement, then it is possible that the timer block
may need to be reset for correct functionality to be restored.
Example: ALTCLK= T
PIOSC
= 62.5ns (16Mhz Trimmed)
T
hclk
= 1us (1Mhz)
4*62.5ns + 2*1us = 2.25us 2.25us/62.5ns = 36 or 0x23
The minimum values for the periodic or one-shot with a match interrupt enabled are:
GPTMTAMATCHR = 0x23 GPTMTAILR = 0x46
GPTMTAMATCHR = 0x23 GPTMTAILR = 0x46
GPTM Clock Configuration (GPTMCC)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0xFC8
Type RW, reset 0x0000.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0xFC8
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ALTCLK
reserved
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0000
RO
reserved
31:1
Alternate Clock Source
Description
Value
System clock (based on clock source and divisor factor
programmed in RSCLKCFG register in the System Control
Module)
programmed in RSCLKCFG register in the System Control
Module)
0
Alternate clock source as defined by ALTCLKCFG register in
System Control Module.
System Control Module.
1
0x0
RW
ALTCLK
0
December 13, 2013
1174
Texas Instruments-Advance Information
General-Purpose Timers