Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
ADC Raw Interrupt Status (ADCRIS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x004
Type RO, reset 0x0000.0000
ADC1 base: 0x4003.9000
Offset 0x004
Type RO, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
INRDC
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INR0
INR1
INR2
INR3
reserved
DMAINR0
DMAINR1
DMAINR2
DMAINR3
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000
RO
reserved
31:17
Digital Comparator Raw Interrupt Status
Description
Value
All bits in the ADCDCISC register are clear.
0
At least one bit in the ADCDCISC register is set, meaning that
a digital comparator interrupt has occurred.
a digital comparator interrupt has occurred.
1
0
RO
INRDC
16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
15:12
SS3 DMA Raw Interrupt Status
Description
Value
The DMA interrupt has not occurred.
0
The sample sequence 3 DMA interrupt is asserted.
1
This bit is cleared by writing a 1 to the
DMAINR3
bit in the ADCISC
register.
0
RO
DMAINR3
11
SS2 DMA Raw Interrupt Status
Description
Value
The DMA interrupt has not occurred.
0
The sample sequence 2 DMA interrupt is asserted.
1
This bit is cleared by writing a 1 to the
DMAINR2
bit in the ADCISC
register.
0
RO
DMAINR2
10
1227
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller