Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
9-Bit Mode Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to a receive address
match.
match.
1
This bit is cleared by writing a 1 to the
9BITIC
bit in the UARTICR
register.
0
RO
9BITMIS
12
End of Transmission Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the transmission of
the last data bit.
the last data bit.
1
This bit is cleared by writing a 1 to the
EOTIC
bit in the UARTICR
register.
0
RO
EOTMIS
11
UART Overrun Error Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to an overrun error.
1
This bit is cleared by writing a 1 to the
OEIC
bit in the UARTICR register.
0
RO
OEMIS
10
UART Break Error Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to a break error.
1
This bit is cleared by writing a 1 to the
BEIC
bit in the UARTICR register.
0
RO
BEMIS
9
UART Parity Error Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to a parity error.
1
This bit is cleared by writing a 1 to the
PEIC
bit in the UARTICR register.
0
RO
PEMIS
8
UART Framing Error Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to a framing error.
1
This bit is cleared by writing a 1 to the
FEIC
bit in the UARTICR register.
0
RO
FEMIS
7
December 13, 2013
1352
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)