Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
The SSICRI1 register bits
DIR
and
MODE
are used to program what operation is needed for the next
data bytes that are being loaded into the FIFO. Table 20-2 on page 1380 shows available modes of
operation:
operation:
Table 20-2. QSSI Transaction Encodings
Operation
MODE
DIR
SSI Legacy operation supporting 4 to 16 data bits
0x0
X
Transmit (TX) Bi-SSI with 8-bits of packet data
0x1
0
Transmit (TX) Quad-SSI with 8-bits of packet data
0x2
0
Transmit (TX) Advanced SSI mode with 8-bits of packet data and write RX FIFO
disabled
disabled
0x3
0
Receive (RX) Bi-SSI with 8-bits of packet data
0x1
1
Receive (RX) Quad-SSI with 8-bits of packet data
0x2
1
Full duplex Advance SSI with 8-bits of packet data
0x3
1
Note:
SPO
= 0 and
SPH
=0 is the only frame structure allowed for Advanced, Bi- and Quad-mode.
Different transactions can follow one another in the FIFOs. The following transaction combinations
are allowed:
are allowed:
■ Legacy SSI mode (if configured for this mode, switching to any other alternate mode is not
recommended)
■ Advanced SSI mode followed by Bi-SSI mode
■ Advanced SSI mode followed by Quad-SSI mode
■ Advanced SSI mode followed by Bi-SSI mode followed by Advanced SSI mode
■ Advanced SSI mode followed by Quad-SSI mode followed by Advanced SSI mode
Note that switching between Quad-SSI and Bi-SSI is not encouraged in a single transaction.
20.3.4
SSInFSS Function
For enhanced modes of operation, the
SSInFss
signal can be programmed to assert low at the
start of each byte transfer for one clock or the entire frame. This is configured by programming the
FSSHLDFRM
bit in the SSICR1 register. The
EOM
bit is also provided to signify end of frame
transmission. This bit is embedded in the TXFIFO entry for use at the interface to deassert
SSInFss
at the appropriate time. The
FSSHLDFRM
bit can also be used when operating in 8-bit Legacy SSI
mode.
The functionality of the
FSSHLDFRM
bit for both Legacy SSI mode and the enhanced modes are as
follows:
December 13, 2013
1380
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)