Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Receive FIFO Request Raw Interrupt Status
Description
Value
No interrupt
0
The trigger level for the RX FIFO has been reached or there is
data in the FIFO and the burst count is zero. Thus, a RX FIFO
request interrupt is pending.
data in the FIFO and the burst count is zero. Thus, a RX FIFO
request interrupt is pending.
1
This bit is cleared by writing a 1 to the
RXIC
bit in the I2CMICR register.
0
RO
RXRIS
9
Transmit Request Raw Interrupt Status
Description
Value
No interrupt
0
The trigger level for the TX FIFO has been reached and more
data is needed to complete the burst. Thus, a TX FIFO request
interrupt is pending.
data is needed to complete the burst. Thus, a TX FIFO request
interrupt is pending.
1
This bit is cleared by writing a 1 to the
TXIC
bit in the I2CMICR register.
0
RO
TXRIS
8
Arbitration Lost Raw Interrupt Status
Description
Value
No interrupt
0
The Arbitration Lost interrupt is pending.
1
This bit is cleared by writing a 1 to the
ARBLOSTIC
bit in the I2CMICR
register.
0
RO
ARBLOSTRIS
7
STOP Detection Raw Interrupt Status
Description
Value
No interrupt
0
The STOP Detection interrupt is pending.
1
This bit is cleared by writing a 1 to the
STOPIC
bit in the I2CMICR
register.
0
RO
STOPRIS
6
START Detection Raw Interrupt Status
Description
Value
No interrupt
0
The START Detection interrupt is pending.
1
This bit is cleared by writing a 1 to the
STARTIC
bit in the I2CMICR
register.
0
RO
STARTRIS
5
Address/Data NACK Raw Interrupt Status
Description
Value
No interrupt
0
The address/data NACK interrupt is pending.
1
This bit is cleared by writing a 1 to the
NACKIC
bit in the I2CMICR
register.
0
RO
NACKRIS
4
December 13, 2013
1468
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface