Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 9: 1-Wire µDMA Control (ONEWIREDMA), offset 0x120
The 1-Wire DMA Control (ONEWIREDMA) register is used to configure the µDMA operation for
1-Wire. This mechanism supports both µDMA write operations, µDMA read operations, small
write/read operations, and scatter-gather support of mixed operations.
1-Wire. This mechanism supports both µDMA write operations, µDMA read operations, small
write/read operations, and scatter-gather support of mixed operations.
Note:
This register is cleared when the
dma_done
signal to the 1-Wire module is asserted by the
µDMA and the
DMA
bit in the ONEWIRERIS register is set.
1-Wire µDMA Control (ONEWIREDMA)
Base 0x400B.6000
Offset 0x120
Type RW, reset 0x0000.0000
Offset 0x120
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RST
DMAOP
SG
reserved
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:4
Scatter-Gather Enable
This bit should be enabled when
DMAOP
= 0x1 and the scatter-gather
method is being used.
This bit self clears after it has performed the µDMA request.
Description
Value
No effect
0
µDMA is requested at start of operation and all requests after
are on completion of transactions.
are on completion of transactions.
1
0
RW
SG
3
µDMA Operation
The programmed operation starts when reset completes if the
RST
bit
in the ONEWIRECS register is set. If
RST
is not set, then write requests
the µDMA immediately and read starts on a write to the ONEWIREDATW
register.
register.
Description
Value
µDMA disabled
0x0
µDMA single read: 1-Wire requests µDMA to read
ONEWIREDATR register after each read transaction.
ONEWIREDATR register after each read transaction.
0x1
µDMA multiple write: 1-Wire requests µDMA to load whenever
the ONEWIREDATW register is empty.
the ONEWIREDATW register is empty.
0x2
µDMA multiple read: An initial read occurs and subsequent
reads start after µDMA has read the ONEWIREDATR register.
reads start after µDMA has read the ONEWIREDATR register.
0x3
0x0
RW
DMAOP
2:1
1531
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller