Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 25: Ethernet MAC MMC Transmit Raw Interrupt Status
(EMACMMCTXRIS), offset 0x108
(EMACMMCTXRIS), offset 0x108
The MAC MMC Transmit Interrupt (EMACMMCTXRIS) register maintains the interrupts generated
when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter
and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and
0xFFFF for 16-bit counter). When the
when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter
and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and
0xFFFF for 16-bit counter). When the
CNTSTPRO
bit is set in the MAC MMC Control
(EMACMMCCTRL) register, interrupts are set but the counter remains at all-ones. The
EMACMMCTXRIS register is a 32-bit wide register. An interrupt bit is cleared when the respective
MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the
respective counter must be read in order to clear the interrupt bit.
EMACMMCTXRIS register is a 32-bit wide register. An interrupt bit is cleared when the respective
MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the
respective counter must be read in order to clear the interrupt bit.
Ethernet MAC MMC Transmit Raw Interrupt Status (EMACMMCTXRIS)
Base 0x400E.C000
Offset 0x108
Type R, reset 0x0000.0000
Offset 0x108
Type R, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
OCTCNT
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
GBF
reserved
SCOLLGF
MCOLLGF
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:21
Octet Counter Interrupt Status
Description
Value
The Ethernet MAC Transmit Octet Count Good
(EMACTXOCTCNTG) register has not reached half of the
maximum value or the maximum value.
(EMACTXOCTCNTG) register has not reached half of the
maximum value or the maximum value.
0
The Ethernet MAC Transmit Octet Count Good
(EMACTXOCTCNTG) register has reached half of the maximum
value or the maximum value.
(EMACTXOCTCNTG) register has reached half of the maximum
value or the maximum value.
1
0x0
RO
OCTCNT
20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
19:16
1709
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller