Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 60: Configuration and Control (CFGCTRL), offset 0xD14
Note:
This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 173).
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 173).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type RW, reset 0x0000.0200
Offset 0xD14
Type RW, reset 0x0000.0200
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BASETHR
MAINPEND
reserved
UNALIGNED
DIV0
reserved
BFHFNMIGN
STKALIGN
reserved
RW
RW
RO
RW
RW
RO
RO
RO
RW
RW
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00
RO
reserved
31:10
Stack Alignment on Exception Entry
Description
Value
The stack is 4-byte aligned.
0
The stack is 8-byte aligned.
1
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
1
RW
STKALIGN
9
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Description
Value
Data bus faults caused by load and store instructions cause a
lock-up.
lock-up.
0
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
caused by load and store instructions.
1
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
0
RW
BFHFNMIGN
8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
7:5
185
December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller