Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 7: LIDD CS1 Configuration (LIDDCS1CFG), offset 0x01C
The LIDD CS1 Configuration (LIDDCS1CFG) register defines the timings for the read and write
strobes with respect to CS1.
strobes with respect to CS1.
LIDD CS1 Configuration (LIDDCS1CFG)
Base 0x4405.0000
Offset 0x01C
Type RW, reset 0x0044.0044
Offset 0x01C
Type RW, reset 0x0044.0044
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RDSU
WRHOLD
WRDUR
WRSU
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GAP
RDHOLD
RDDUR
RDSU
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Write Strobe (WR) Set-Up Cycles
When performing a write access, this field defines the number of
LCDMCLK
cycles that Data Bus/Pad Output Enable, ALE, DIR, and CS1
have to be ready before WR (
LCDLP
) is asserted. The minimum value
is 0x0.
0x0
RW
WRSU
31:27
Write Strobe (WR) Duration Cycles
Field value defines the number of
LCDMCLK
cycles for which WR (
LCDLP
)
is held active when performing a write access. The minimum value is
0x1.
0x1.
0x2
RW
WRDUR
26:21
Write Strobe (WR) Hold cycles.
Field value defines the number of
LCDMCLK
cycles for which Data
Bus/Pad Output Enable, ALE, the DIR, and CS1 signals are held after
WR (
WR (
LCDLP
) is deasserted when performing a write access. The
minimum value is 0x1.
0x2
RW
WRHOLD
20:17
Read Strobe (RD) Set-Up cycles.
When performing a read access, this field defines the number of
LCDMCLK
cycles that Data Bus/Pad Output Enable, ALE, the DIR, and
CS1 signals have to be ready before RD (
LCDCP
) is asserted.
0x0
RW
RDSU
16:12
Read Strobe (RD) Duration cycles.
Field value defines the number of LCDMCLK cycles for which RD
(
(
LCDCP
) is held active when performing a read access. The minimum
value is 0x1.
0x1
RW
RDDUR
11:6
Read Strobe (RD) Hold cycles.
Field value defines the number of
LCDMCLK
cycles for which Data
Bus/Pad Output Enable, ALE, DIR, and CS1 signals are held after RD
(
(
LCDCP
) is deasserted when performing a read access. The minimum
value is 0x1.
0x1
RW
RDHOLD
5:2
Field value defines the number of
LCDMCLK
cycles (GAP + 1) between
the end of one CS1 (
LCDAC
) device access and the start of another CS0
(
LCDAC
) device access unless the two accesses are both reads. In this
case, this delay is not incurred. The minimum value is 0x0.
0x0
RW
GAP
1:0
1879
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller