Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
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제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
This bit controls the bytelane ordering of the data on the output of the
DMA module. It works in conjunction with the big-endian bit. See the
big-endian description for configuration guidelines.
DMA module. It works in conjunction with the big-endian bit. See the
big-endian description for configuration guidelines.
0
RW
BYTESWAP
3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
2
Big Endian Enable
Use this bit when the processor is operating in Big Endian mode and
writes to the frame buffers are less than 32-bits wide. Only in this
scenario do we need to change the byte alignment for data coming into
the FIFO from the frame buffer.
writes to the frame buffers are less than 32-bits wide. Only in this
scenario do we need to change the byte alignment for data coming into
the FIFO from the frame buffer.
Description
Value
Big Endian reordering disabled.
0
Big Endian reordering enabled.
1
The
BIGEND
and
BYTESWAP
bits control the byte lane ordering of the
data on the output of the DMA module.
0
RW
BIGDEND
1
Frame Mode
Description
Value
One frame buffer (FB0 only) used
0
Two frame buffers used,. DMA ping-pongs between FB0 and
FB1 in this mode
FB1 in this mode
1
0
RW
FMODE
0
December 13, 2013
1894
Texas Instruments-Advance Information
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