Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
complete switch sequence should consist of the following transactions on the
TCK
/
SWCLK
and
TMS
/
SWDIO
signals:
1.
Send at least 50
TCK
/
SWCLK
cycles with
TMS
/
SWDIO
High to ensure that both JTAG and SWD
are in their reset states.
2.
Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on
TMS/SWDIO
.
3.
Send at least 50
TCK
/
SWCLK
cycles with
TMS
/
SWDIO
High to ensure that if SWJ-DP was already
in SWD mode before sending the switch sequence, the SWD goes into the line reset state.
To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating
mode, perform a SWD READID operation. The ID value can be compared against the device's
known ID to verify the switch.
mode, perform a SWD READID operation. The ID value can be compared against the device's
known ID to verify the switch.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit
external debug hardware must send a switch command to the microcontroller. The 16-bit
TMS/SWDIO
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the
TCK
/
SWCLK
and
TMS
/
SWDIO
signals:
1.
Send at least 50
TCK
/
SWCLK
cycles with
TMS
/
SWDIO
High to ensure that both JTAG and SWD
are in their reset states.
2.
Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on
TMS/SWDIO
.
3.
Send at least 50
TCK
/
SWCLK
cycles with
TMS
/
SWDIO
High to ensure that if SWJ-DP was already
in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset
state.
state.
To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the device's known IDCODE to verify the switch.
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the device's known IDCODE to verify the switch.
4.4
Initialization and Configuration
After a Power-On-Reset or an external reset (
RST
), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (
PC[3:0]
) for their alternate function using the GPIOAFSEL register.
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (
on the four JTAG pins (
PC[3:0]
) should be returned to their default settings.
4.5
Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
225
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller