Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt in the
Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 272).
Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 272).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type RW1C, reset 0x0000.0000
Offset 0x058
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
BORMIS
reserved
MOFMIS
reserved
PLLLMIS
reserved
MOSCPUPMIS
reserved
RO
RW1C
RO
RW1C
RO
RO
RW1C
RO
RW1C
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00
RO
reserved
31:9
MOSC Power Up Masked Interrupt Status
Description
Value
When read, a 0 indicates that sufficient time has not passed for
the MOSC PLL to lock.
the MOSC PLL to lock.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the MOSC PLL
to lock.
signaled because sufficient time has passed for the MOSC PLL
to lock.
Writing a 1 to this bit clears it and also the
MOSCPUPRIS
bit in
the RIS register.
1
0
RW1C
MOSCPUPMIS
8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
7
PLL Lock Masked Interrupt Status
Description
Value
When read, a 0 indicates that sufficient time has not passed for
the PLL to lock.
the PLL to lock.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the PLL to lock.
signaled because sufficient time has passed for the PLL to lock.
Writing a 1 to this bit clears it and also the
PLLLRIS
bit in the
RIS register.
1
0
RW1C
PLLLMIS
6
December 13, 2013
276
Texas Instruments-Advance Information
System Control