Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 135: General-Purpose Input/Output Deep-Sleep Mode Clock Gating
Control (DCGCGPIO), offset 0x808
Control (DCGCGPIO), offset 0x808
The DCGCGPIO register provides software the capability to enable and disable GPIO modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.
Important: This register should be used to control the clocking for the GPIO modules.
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO)
Base 0x400F.E000
Offset 0x808
Type RW, reset 0x0000.0000
Offset 0x808
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D16
D17
reserved
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:18
GPIO Port T Deep-Sleep Mode Clock Gating Control
Description
Value
GPIO Port T is disabled in deep-sleep mode.
0
Enable and provide a clock to GPIO Port T in deep-sleep mode.
1
0
RW
D17
17
GPIO Port S Deep-Sleep Mode Clock Gating Control
Description
Value
GPIO Port S is disabled in deep-sleep mode.
0
Enable and provide a clock to GPIO Port S in deep-sleep mode.
1
0
RW
D16
16
GPIO Port R Deep-Sleep Mode Clock Gating Control
Description
Value
GPIO Port R is disabled in deep-sleep mode.
0
Enable and provide a clock to GPIO Port R in deep-sleep mode.
1
0
RW
D15
15
GPIO Port Q Deep-Sleep Mode Clock Gating Control
Description
Value
GPIO Port Q is disabled in deep-sleep mode.
0
Enable and provide a clock to GPIO Port Q in deep-sleep mode.
1
0
RW
D14
14
December 13, 2013
450
Texas Instruments-Advance Information
System Control