Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트

the arbitration size, it is possible to control exactly how many items are transferred to or from a
peripheral each time it makes a μDMA service request.

Each DMA channel has up to nine possible assignments which are selected using the DMA Channel
Map Select n (DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel.

Table 9-1 on page 709 shows the µDMA channel mapping. The Enc. column shows the encoding
for the respective DMACHMAPn bit field. Encodings 0x9-0xF are reserved. To support legacy
software which uses the DMA Channel Assignment (DMACHASGN) register, Enc. 0 is equivalent
to a DMACHASGN bit being clear, and Enc. 1 is equivalent to a DMACHASGN bit being set. If the
DMACHASGN register is read, bit fields return 0 if the corresponding DMACHMAPn register field
value are equal to 0, otherwise they return 1 if the corresponding DMACHMAPn register field values
are not equal to 0. The Type indication in the table indicates if a particular peripheral uses a single
request (S), burst request (B) or either (SB).

Channels or encodings marked as reserved cannot be used for µDMA transfers. Channels
designated in the table as only "Software" are dedicated software channels. When only one
software request is required in an application, dedicated software channels can be used.
If multiple software requests in code are required, then peripheral channel software requests
should be used for proper µDMA completion acknowledgement.

-

Reserved

-

Reserved

SB

B

I2C0 RX

-

Reserved

-

Reserved

B

GPTimer
4A

-

Reserved

SB

UART2
RX

-

Reserved

0

-

Reserved

-

Reserved

SB

B

I2C0 TX

-

Reserved

-

Reserved

B

GPTimer
4B

-

Reserved

SB

UART2
TX

-

Reserved

1

-

Reserved

-

Reserved

SB

B

I2C1RX

-

Reserved

-

Reserved

-

Reserved

-

Reserved

B

GPTimer
3A

-

Reserved

2

-

Reserved

-

Reserved

SB

B

I2C1 TX

-

Reserved

-

Reserved

S

Software

-

Reserved

B

GPTimer
3B

-

Reserved

3

-

Reserved

-

Reserved

SB

B

I2C2 RX

B

SHA/MD5

0 Cin

-

Reserved

B

GPIO A

-

Reserved

B

GPTimer
2A

-

Reserved

4

-

Reserved

-

Reserved

SB

B

I2C2 TX

B

SHA/MD5

0 Din

-

Reserved

B

GPIO B

-

Reserved

B

GPTimer
2B

-

Reserved

5

-

Reserved

-

Reserved

-

Reserved

B

SHA/MD5

0 Cout

SB

B

I2C0 RX

B

GPIO C

SB

UART5
RX

B

GPTimer
2A

-

Reserved

6

-

Reserved

-

Reserved

-

Reserved

-

Reserved

SB

B

I2C0 TX

B

GPIO D

SB

UART5
TX

B

GPTimer
2B

-

Reserved

7

-

Reserved

-

Reserved

-

Reserved

-

Reserved

SB

B

I2C1RX

B

GPTimer
5A

-

Reserved

SB

UART1
RX

SB

UART0
RX

8

-

Reserved

-

Reserved

-

Reserved

-

Reserved

SB

B

I2C1 TX

B

GPTimer
5B

-

Reserved

SB

UART1
TX

SB

UART0
TX

9

-

Reserved

B

GPTimer
6A

-

Reserved

-

Reserved

SB

B

I2C2 RX

-

Reserved

SB

UART6
RX

SB

SSI1 RX

SB

SSI0 RX

10