Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 34: EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308
Important: The
MODE
field in the EPICFG register configures whether EPI Host Bus mode is enabled.
For EPIHB8CFG3 to be valid, the
MODE
field must be 0x2.
EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3)
Base 0x400D.0000
Offset 0x308
Type RW, reset 0x0008.0000
Offset 0x308
Type RW, reset 0x0008.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
ALEHIGH
RDHIGH
WRHIGH
reserved
RO
RO
RO
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MODE
reserved
RDWS
WRWS
reserved
RW
RW
RO
RO
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000
RO
reserved
31:22
CS2n WRITE Strobe Polarity
This field is used if the
CSBAUD
bit is enabled in EPIHB8CFG2.
Description
Value
The WRITE strobe for CS2n accesses is WRn (active Low).
0
The WRITE strobe for CS2n accesses is WR (active High).
1
0
RW
WRHIGH
21
CS2n READ Strobe Polarity
This field is used if the
CSBAUD
bit is enabled in EPIHB8CFG2.
Description
Value
The READ strobe for CS2n accesses is RDn (active Low).
0
The READ strobe for CS2n accesses is RD (active High).
1
0
RW
RDHIGH
20
CS2n ALE Strobe Polarity
This field is used if the
CSBAUD
bit is enabled in EPIHB8CFG2.
Description
Value
The address latch strobe for CS2n accesses is ADVn (active
Low).
Low).
0
The address latch strobe for CS2n accesses is ALE (active
High).
High).
1
1
RW
ALEHIGH
19
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
18:8
December 13, 2013
946
Texas Instruments-Advance Information
External Peripheral Interface (EPI)