Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used
to specify parameters of a μDMA transfer.
to specify parameters of a μDMA transfer.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
not the μDMA module base address.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type RW, reset -
Offset 0x008
Type RW, reset -
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ARBSIZE
SRCPROT0
reserved
DSTPROT0
reserved
SRCSIZE
SRCINC
DSTSIZE
DSTINC
RW
RW
RW
RO
RO
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Type
-
-
0
-
-
0
0
0
-
-
-
-
-
-
-
-
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XFERMODE
NXTUSEBURST
XFERSIZE
ARBSIZE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reset
Description
Reset
Type
Name
Bit/Field
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (
of the destination size (
DSTSIZE
).
Description
Value
Byte
Increment by 8-bit locations
0x0
Half-word
Increment by 16-bit locations
0x1
Word
Increment by 32-bit locations
0x2
No increment
Address remains set to the value of the Destination Address
End Pointer (
End Pointer (
DMADSTENDP
) for the channel
0x3
-
RW
DSTINC
31:30
December 13, 2013
734
Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)