Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.6
Configurations After Reset
The following sections provide details on configuring the device after reset.
Multiplexed pin are configured both at and after reset.
, Device and Peripheral Configurations
at Device Reset, discusses multiplexed pin control at reset. For more details on multiplexed pins control
after reset, see
after reset, see
, Multiplexed Pin Configurations.
4.6.1
Switch Central Resource (SCR) Bus Priorities
Prioritization within the Switched Central Resource (SCR) is programmable for each master. The register
bit fields and default priority levels for DM6467T bus masters are shown in
bit fields and default priority levels for DM6467T bus masters are shown in
, DM6467T Default
Bus Master Priorities. The priority levels should be tuned to obtain the best system performance for a
particular application. Lower values indicate higher priority. For most masters, their priority values are
programmed at the system level by configuring the MSTPRI0, MSTPRI1, and MSTPRI2 registers. Details
on the MSTPRI0/1/2 registers are shown in
particular application. Lower values indicate higher priority. For most masters, their priority values are
programmed at the system level by configuring the MSTPRI0, MSTPRI1, and MSTPRI2 registers. Details
on the MSTPRI0/1/2 registers are shown in
, and
Table 4-14. DM6467T Default Bus Master Priorities
Priority Bit Field
Bus Master
Default Priority Level
VP0P
VPIF Capture
1 (MSTPRI2 Register)
VP1P
VPIF Display
1 (MSTPRI2 Register)
TSIF0P
TSIF0
1 (MSTPRI2 Register)
TSIF1P
TSIF1
1 (MSTPRI2 Register)
EDMATC0P
EDMATC0
2 (MSTPRI2 Register)
EDMATC1P
EDMATC1
2 (MSTPRI2 Register)
EDMATC2P
EDMATC2
2 (MSTPRI2 Register)
EDMATC3P
EDMATC3
2 (MSTPRI2 Register)
HDVICP0P
HDVICP0 (CFG)
(1)
3 (MSTPRI0 Register)
HDVICP1P
HDVICP1 (CFG)
(1)
3 (MSTPRI0 Register)
ARMINSTP
ARM926 (INST)
4 (MSTPRI0 Register)
ARMDATAP
ARM926 (DATA)
4 (MSTPRI0 Register)
DSPDMAP
C64x+ DSP (DMA)
4 (MSTPRI0 Register)
DSPCFGP
C64x+ DSP (CFG)
(1)
4 (MSTPRI0 Register)
VDCEP
VDCE
4 (MSTPRI1 Register)
EMACP
EMAC
5 (MSTPRI1 Register)
USBP
USB2.0
5 (MSTPRI1 Register)
ATAP
ATA
5 (MSTPRI1 Register)
VLYNQP
VLYNQ
5 (MSTPRI1 Register)
PCIP
PCI
6 (MSTPRI1 Register)
HPIP
HPI
6 (MSTPRI1 Register)
(1)
The C64x+ DSP (CFG), HDVICP0 (CFG), and HDVICP1 (CFG) priority values are not actually used by the DMSoC infrastructure –
which gives equal weight round-robin priority to accesses from these three masters. Therefore, the priority settings for these three
masters in the MSTPRI0 register have no effect.
which gives equal weight round-robin priority to accesses from these three masters. Therefore, the priority settings for these three
masters in the MSTPRI0 register have no effect.
102
Device Configurations
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