Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.7
Multiplexed Pin Configurations
DM6467T makes extensive use of pin multiplexing to accommodate a large number of peripheral function
in the smallest possible package, providing the ultimate flexibility for end applications.
in the smallest possible package, providing the ultimate flexibility for end applications.
The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsiblie for controlling
all pin multiplexing functions on the DM6467T. The default setting of some of the PINMUX0 and PINMUX1
bit fields are configured by configuration pins latched at reset (see
all pin multiplexing functions on the DM6467T. The default setting of some of the PINMUX0 and PINMUX1
bit fields are configured by configuration pins latched at reset (see
, Device and Peripheral
Configurations at Device Reset). After reset, software may program the PINMUX0 and PINMUX1 registers
to switch pin functionalities.
to switch pin functionalities.
The following peripherals have multiplexed pins: VPIF, TSIF0, TSIF1, CRGEN0, CRGEN1, EMIFA, PCI,
HPI, ATA, PWM0, PWM1, UART0, UART1, UART2, Audio Clock Selector, the USB USB_DRVVBUS pin,
and GPIO.
HPI, ATA, PWM0, PWM1, UART0, UART1, UART2, Audio Clock Selector, the USB USB_DRVVBUS pin,
and GPIO.
4.7.1
Pin Muxing Selection At Reset
This section summarizes pin mux selection at reset.
The configuration pins CS2BW and PCIEN, latched at device reset, determine the default pin muxing. For
more details on the default pin muxing at reset, see
more details on the default pin muxing at reset, see
, Configurations At Reset.
4.7.2
Pin Muxing Selection After Reset
The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions.
Some pin functions require a combination of PINMUX0/PINMUX1 bit fields. For more details on the
combination of the PINMUX bit fields that control each muxed pin, see
Some pin functions require a combination of PINMUX0/PINMUX1 bit fields. For more details on the
combination of the PINMUX bit fields that control each muxed pin, see
, Pin Multiplexing
Details.
This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed
discussion on how to program each Pin Mux Block, see
discussion on how to program each Pin Mux Block, see
, Pin Multiplexing Details.
4.7.2.1
PINMUX0 Register Description
The Pin Multiplexing 0 Register controls the pin function in the EMIFA/ATA/HPI/PCI, TSIF0, TSIF1,
CRGEN, Block. The PINMUX0 register format is shown in
CRGEN, Block. The PINMUX0 register format is shown in
and the bit field descriptions are
given in
. Some muxed pins are controlled by more than one PINMUX bit field. For the
combination of the PINMUX bit fields that control each muxed pin, see
, Pin Multiplexing
Details. For more information on the block pin muxing and pin-by-pin muxing control, see specific block
muxing section (for example, for CRGEN Pin Mux Control, see
muxing section (for example, for CRGEN Pin Mux Control, see
, CRGEN Signal Muxing).
31
30
29
28
27
26
24
23
22
21
20
19
18
17
16
VBUSDIS
STCCK
AUDCK1
AUDCK0
RSV
CRGMUX
TSSOMUX
TSSIMUX
TSPOMUX
TSPIMUX
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-000
R/W-00
R/W-00
R/W-00
R/W-00
15
6
5
4
3
2
1
0
RESERVED
RSV
RESERVED
PCIEN
HPIEN
ATAEN
R-0000 0000 00
R/W-0
R-0
R/W-L
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-18. PINMUX0 Register [0x01C4 0000]
110
Device Configurations
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