Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 4-22. PINMUX0 Register Bit Descriptions
BIT
NAME
DESCRIPTION
This bit disables USB_DRVVBUS output.
31
VBUSDIS
0 = USB_DRVVBUS function selected.
1 = GP[22] function selected.
1 = GP[22] function selected.
This bit enables STC Source Clock input.
30
STCCK
0 = GP[4] function selected.
1 = STC_CLKIN function selected.
1 = STC_CLKIN function selected.
This bit enables AUDIO_CLK1 output.
29
AUDCK1
0 = GP[2] function selected.
1 = AUDIO_CLK1 function selected.
1 = AUDIO_CLK1 function selected.
This bit enables AUDIO_CLK0 output.
28
AUDCK0
0 = GP[3] function selected.
1 = AUDIO_CLK0 function selected.
1 = AUDIO_CLK0 function selected.
27
RSV
Reserved. Read returns "0".
CRGEN Pin Mux Control (see
, CRGEN Signal Muxing).
000 = No CRGEN signals enabled.
001 = CRGEN1 selection enabled (muxed with UART2 data).
010 = Reserved (no CRGEN signals enabled).
001 = CRGEN1 selection enabled (muxed with UART2 data).
010 = Reserved (no CRGEN signals enabled).
26:24
CRGMUX
011 = Reserved (no CRGEN signals enabled).
100 = CRGEN0 selection enabled (muxed with UCTS2 and PWM0).
101 = CRGEN0 and CRGEN1 selection enabled.
110 = CRGEN0 selection enabled (muxed with UART2 data).
111 = Reserved (no CRGEN signals enabled).
100 = CRGEN0 selection enabled (muxed with UCTS2 and PWM0).
101 = CRGEN0 and CRGEN1 selection enabled.
110 = CRGEN0 selection enabled (muxed with UART2 data).
111 = Reserved (no CRGEN signals enabled).
TSIF1 Serial Output Pin Mux Control (see
(1)
, TSSO Signal Muxing).
0x = No TS1 output signals enabled.
23:22
TSSOMUX
10 = TS1 output selection enabled (muxed on VP_DOUT pins).
11 = TS1 output selection enabled (muxed on URIN0, UCTS2, PWM0, and PWM1 pins).
11 = TS1 output selection enabled (muxed on URIN0, UCTS2, PWM0, and PWM1 pins).
TSIF1 Serial Input Pin Mux Control (see
, TSIF1 Input Signal Muxing).
00 = No TS1 input signals enabled.
21:20
TSSIMUX
01 = TS1 input selection enabled (muxed on UART0 pins).
10 = TS1 input selection enabled (muxed on VP_DOUT pins).
11 = TS1 input selection enabled (muxed on VP_DIN pins).
10 = TS1 input selection enabled (muxed on VP_DOUT pins).
11 = TS1 input selection enabled (muxed on VP_DIN pins).
TSIF0 Parallel/Serial Output Pin Mux Control (see
, TSIF0 Output Signal Muxing).
0x = No TS0 output signals enabled.
19:18
TSPOMUX
10 = TS0 parallel output muxing enabled (muxed with VP_DIN pins).
11 = TS0 serial output muxing enabled (muxed TS0_DOUT7 with UTXD1).
11 = TS0 serial output muxing enabled (muxed TS0_DOUT7 with UTXD1).
TSIF0 Parallel/Serial Input Pin Mux Control (see
, TSIF0 Input Signal Muxing).
0x = No TS0 signals enabled.
17:16
TSPIMUX
10 = TS0 parallel input muxing enabled (muxed with VP_DIN pins).
11 = TS0 serial input muxing enabled (muxed TS0_DIN7 with URXD1).
11 = TS0 serial input muxing enabled (muxed TS0_DIN7 with URXD1).
15:6
RESERVED
Reserved. Read returns "0".
Reserved. Read returns "0". Note: For proper device operation, when writing to this bit, only a "0"
5
RESERVED
should be written.
4:3
RESERVED
Reserved. Read returns "0".
PCI Function Enable (see
, PCI, HPI, EMIFA and ATA Pin Muxing).
2
PCIEN
Default value is determined by PCIEN boot configuration pin.
1
HPIEN
HPI Function Enable (see
, PCI, HPI, EMIFA and ATA Pin Muxing).
0
ATAEN
ATA Function Enable (see
, PCI, HPI, EMIFA and ATA Pin Muxing).
(1)
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see
pullup/pulldown resistors are required, see
, Pullup/Pulldown Resistors.
Copyright © 2009–2012, Texas Instruments Incorporated
Device Configurations
111
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