Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트

SPRS605C – JULY 2009 – REVISED JUNE 2012

During device reset, all other pins are controlled by the default peripheral. The default peripheral is
determined by the default settings of the PINMUX0 or PINMUX1 registers.

Some of the PINMUX0/PINMUX1 settings are determined by configuration pins latched at reset. To
determine the reset behavior of these pins, see

, Multiplexed Pin Configurations and read the

rest of the this subsection to understand how that default peripheral controls the pin.

The reset behaviors for all these other pins during all boot modes, except PCI Boot, are categorized as
follows (also see

and

in

, Reset Electrical Data/Timing):

•

DDR2 Z Group: DDR_DQS[3:0], DDR_DQS[3:0], DDR_D[31:0], DDR_DQGATE1, DDR_DQGATE3

•

DDR_CLK,

DDR_CKE,

DDR_ODT0,

DDR_A[14:0],

DDR_DQGATE0,

DDR_DQGATE2

•

DDR2 High Group: DDR_CLK, DDR_CS, DDR_WE, DDR_RAS, DDR_CAS

•

DDR2 Z/High Group: DDR_DQM[3:0]

•

DDR2 Low/High Group: DDR_BA[2:0]

•

Z Group: These pin are 3-stated by default, and these pins remain 3-stated throughout POR or
RESET assertion. When POR or RESET is deasserted, these pins remain 3-stated until configured
otherwise

by

their

respective

peripheral

(after

the

peripheral

is

enabled

by

the

PSC).

PCI_CLK/GP[10],

PCI_INTA/EM_WAIT2,

DIOW/GP[20]/EM_WAIT4,

IORDY/GP[21]/EM_WAIT3,

PCI_AD[15:0]/HD[15:0]/EM_D[15:0], RFTCLK, GMTCLK, MTCLK, MTXD[7:0], MTXEN, MCOL, MCRS,
MRCLK,

MRXD[7:0],

MRXDV,

MRXER,

MDCLK,

MDIO,

URXD0/TS1_DIN,

UTXD0/URCTX0/TS1_PSTIN,

URTS0/UIRTX0/TS1_EN_WAITO,

UCTS0/USD0,

UDTR0/TS0_ENAO/GP[36],

UDSR0/TS0_PSTO/GP[37],

UDCD0/TS0_WAITIN/GP[38],

URIN0/GP[8]/TS1_WAITIN,

URXD1/TS0_DIN7/GP[23],

UTXD1/URCTX1/TS0_DOUT7/GP[24],

URTS1/UIRTX1/TS0_WAITO/GP[25],

UCTS1/USD1/TS0_EN_WAITO/GP[26],

URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI,

UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO,

URTS2/UIRTX2/TS0_PSTIN/GP[41],

UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO,

ACLKR0,

AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0, AXR0[3:0], AMUTE0, AMUTEIN0, ACLKX1,
AHCLKX1, AXR1[0], SCL, SDA, SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_MISO, SPI_MOSI,
PWM0/CRG0_PO/TS1_ENAO,

PWM1/TS1_DOUT,

VLYNQ_CLOCK,

VLYNQ_SCRUN,

VLYNQ_TXD[3:0], VLYNQ_RXD[3:0], USB_DRVVBUS/GP[22], TINP0L, TINP0U, TOUT0L, TOUT0U,
TINP1L,

TOUT1L,

TOUT1U,

TOUT2,

TS0_CLKIN,

TS1_CLKIN,

VP_CLKIN0,

VP_CLKIN1,

VP_DIN15_VSYNC/TS0_DIN7,

VP_DIN14_HSYNC/TS0_DIN6,

VP_DIN13_FIELD/TS0_DIN5,

VP_DIN12/TS0_DIN4,

VP_DIN11/TS0_DIN3,

VP_DIN10/TS0_DIN2,

VP_DIN9/TS0_DIN1,

VP_DIN8/TS0_DIN0,

VP_DIN7/TS0_DOUT7/TS1_DIN,

VP_DIN6/TS0_DOUT6/TS1_PSTIN,

VP_DIN5/TS0_DOUT5/TS1_EN_WAITO,

VP_DIN4/TS0_DOUT4/TS1_WAITO,

VP_DIN3/TS0_DOUT3,

VP_DIN2/TS0_DOUT2,

VP_DIN1/TS0_DOUT1,

VP_DIN0/TS0_DOUT0,

VP_CLKIN2, VP_CLKIN3/TS1_CLKO, VP_CLKO2, VP_CLKO3/TS0_CLKO, VP_DOUT15/TS1_DIN,
VP_DOUT14/TS1_PSTIN,

VP_DOUT13/TS1_EN_WAITO,

VP_DOUT12/TS1_WAITO,

VP_DOUT11/TS1_DOUT,

VP_DOUT10/TS1_PSTO,

VP_DOUT9/TS1_ENAO,

VP_DOUT8/TS1_WAITIN, VP_DOUT7, GP[0], GP[1], GP[2]/AUDIO_CLK1, GP[3]/AUDIO_CLK0,
GP[4]/STC_CLKIN,

GP[5],

GP[6],

GP[7],

TIMS,

TDO,

TDI,

TCK,

TRST,

EMU1,

EMU0,

DEV_MXI/DEV_CLKIN, AUX_MXI/AUX_CLKIN

•

Low Group: These pins are low by default, and remain low until configured otherwise by their
respective

peripheral

(after

the

peripheral

is

enabled

by

the

PSC).

PCI_RST/DA2/GP[13]/EM_A[22],

PCI_IDSEL/HDDIR/EM_R/W,

PCI_IRDY/HRDY/EM_A[17],

PCI_TRDY/HHWIL/EM_A[16],

PCI_CBE1/ATA_CS1/GP[32]/EM_A[19],

PCI_CBE0/ATA_CS0/GP[33]/EM_A[18], PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0], CLKOUT0,
RTCLK,

188

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