Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
1
4
5
TSx_CLKIN
(Positive Edge Clocking)
TSx_CTL/
TSx_DATA
(A)
3
3
TSx_CLKIN
(Negative Edge Clocking)
2
2
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.12.4 Transport Stream Interface (TSIF) Electrical Data/Timing
Table 7-52. Timing Requirements for TSIF Input (see
-1G
SERIAL
PARALLEL
NO.
UNIT
INPUT
INPUT
(1)
MIN
MAX
MIN
MAX
1
t
c(TSCLKIN)
Cycle time, TSx_CLKIN
10
16.7
ns
2
t
w(TSCLKIN)
Pulse duration, TSx_CLKIN high/low
(2)
0.4C
0.4C
ns
3
t
t(TSCLKIN)
Transition time, TSx_CLKIN
3
(3)
3
(3)
ns
All Others
4
4
ns
Setup time, TSx_CTL/TSx_DATA
(4)
input valid
4
t
su(TSDATAIN-TSCLKINV)
TSx_WAIT
before TSx_CLKIN edge
13
13
ns
IN
Hold time, TSx_CTL/TSx_DATA
(4)
input valid after
5
t
h(TSCLKINV-TSDATAIN)
0
0
ns
TSx_CLKIN edge
(1)
TSIF1 supports SERIAL INPUT mode only.
(2)
C = TSx_CLKIN period (cycle time) in ns.
(3)
For a 4-inch transmission line with 4-pF load capacitance at the device pin.
(4)
TSx_CTL/TSx_DATA input includes: TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0] for a parallel input. For a serial
input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and TS0_DIN7 or TS1_DIN.
input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and TS0_DIN7 or TS1_DIN.
A.
TSx_CTL/TSx_DATA input includes: TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0] for a parallel
input. For a serial input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and
TS0_DIN7 or TS1_DIN.
input. For a serial input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and
TS0_DIN7 or TS1_DIN.
Figure 7-45. TSIF Input Timing
Table 7-53. Switching Characteristics Over Recommended Operating Conditions for TSIF Output
(see
)
-1G
SERIAL
PARALLEL
NO.
UNIT
OUTPUT
OUTPUT
(1)
MIN
MAX
MIN
MAX
6
t
c(TSCLKO)
Cycle time, TSx_CLKO
10
16.7
ns
7
t
w(TSCLKO)
Pulse duration, TSx_CLKO high/low
(2)
0.4C
0.4C
ns
8
t
t(TSCLKO)
Transition time, TSx_CLKO
3
(3)
3
(3)
ns
(1)
TSIF1 supports SERIAL OUTPUT mode only.
(2)
C = TSx_CLKO period (cycle time) in ns.
(3)
For a 4-inch transmission line with 4-pF load capacitance at the device pin.
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Peripheral Information and Electrical Specifications
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