Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.13 Clock Recovery Generator (CRGEN)
Each TSIF module has an associated CRGEN module which can adjust the local system time clock based
upon the received Program Clock Reference (PCR) packets. CRGEN0 may only be used with TSIF 0 and
CRGEN 1 may only be used with TSIF 1.
upon the received Program Clock Reference (PCR) packets. CRGEN0 may only be used with TSIF 0 and
CRGEN 1 may only be used with TSIF 1.
Each CRGEN module features:
•
Automatic load of received PCR packet values from associated TSIF module
•
Local System Time Clock (STC) counter
•
PCR/STC difference generator (subtractor)
•
Loop Filter (LPF)
•
1-bit sigma/delta modulator digital-to-analog converter (DAC) output for external VCXO control
7.13.1 CRGEN Peripheral Register Description(s)
The CRGEN0 and CRGEN1 registers are shown in
and
, respectively.
Table 7-54. CRGEN0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01C2 6000
PID
CRGEN Peripheral Identification Register
0x01C2 6004
CONTROL
CRGEN control register
0x01C2 6008
STC_HI
System Time Clock (STC) current value (upper 17 bits)
0x01C2 600C
STC_LO
STC current value (lower 16 bits plus extension)
0x01C2 6010
STC_VAL_HI
STC value (upper 17 bits) on TSIF0 PCR packet detection
STC value (lower 16 bits plus extension) on TSIF0 PCR packet
0x01C2 6014
STC_VAL_LO
detection
Program Clock Reference (PCR) value (upper 17 bits) from
0x01C2 6018
PCR_HI
TSIF0 Receive packet
PCR value (lower 16 bits plus extension) from TSIF0 Receive
0x01C2 601C
PCR_LO
packet
0x01C2 6020
PCR_PKT_STAT
PCR packet status
0x01C2 6024
LOOP_FILTER
Loop filter (LPF) interface
Offset value of the STC counter for the higher (upper) 17 bits.
0x01C2 6028
STC_OFFSET_HI
This value is detected in the STC counter with the first PCR
loading pulse signal.
loading pulse signal.
Offset value of the STC counter for the lower 16 bits. The role
0x01C2 602C
STC_OFFSET_LO
of this register is same as the STC_LO register 0x01C2 600C.
0x01C2 6030 - 0x01C2 603F
-
Reserved
0x01C2 6040
INTEN
Interrupt enable
0x01C2 6044
INTEN_SET
Interrupt enable set
0x01C2 6048
INTEN_CLR
Interrupt enable clear
0x01C2 604C
INTSTAT
Interrupt status
0x01C2 6050
INTSTAT_CLR
Interrupt status clear
0x01C2 6054
EMU_CTRL
Emulation control
0x01C2 6058 - 0x01C2 607F
-
Reserved
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
237
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