Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-85. USB2.0 DMA Master Memory Map (continued)
SIZE
START ADDRESS
END ADDRESS
USB2.0 DMA ACCESS
(BYTES)
0x8000 0000
0x9FFF FFFF
512M
DDR2 Memory Controller
0xA000 0000
0xBFFF FFFF
512M
Reserved
0xC000 0000
0xFFFF FFFF
1G
Reserved
7.19.2 USB2.0 Device-Specific Information
The DM6467T USBCTL register (0x01C4 00034) is part of the System Module Registers. The USBCTL
register controls the USB data polarity, host/peripheral mode, and VBUS sense, along with the PHY power
and clock good, PHY PLL suspend override, and PHY power down. For more detailed information on the
USBCTL System Module Register, see
register controls the USB data polarity, host/peripheral mode, and VBUS sense, along with the PHY power
and clock good, PHY PLL suspend override, and PHY power down. For more detailed information on the
USBCTL System Module Register, see
, Peripheral Selection After Device Reset
For more detailed information on the USB2.0 peripheral, see the TMS320DM646x DMSoC Universal
Serial Bus (USB) Controller User's Guide (literature number
Serial Bus (USB) Controller User's Guide (literature number
270
Peripheral Information and Electrical Specifications
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