Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
VLYNQ_CLOCK
3
1
2
4
4
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.21.3 VLYNQ Electrical Data/Timing
Table 7-96. Timing Requirements for VLYNQ_CLOCK Input (see
-1G
NO.
UNIT
MIN
MAX
1
t
c(VCLK)
Cycle time, VLYNQ_CLOCK
9.6
ns
2
t
w(VCLKH)
Pulse duration, VLYNQ_CLOCK high
3
ns
3
t
w(VCLKL)
Pulse duration, VLYNQ_CLK low
3
ns
4
t
t(VCLK)
Transition time, VLYNQ_CLOCK
3
ns
Table 7-97. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLOCK
Output (see
-1G
NO.
PARAMETER
UNIT
MIN
MAX
1
t
c(VCLK)
Cycle time, VLYNQ_CLOCK
9.6
ns
2
t
w(VCLKH)
Pulse duration, VLYNQ_CLOCK high
4
ns
3
t
w(VCLKL)
Pulse duration, VLYNQ_CLOCK low
4
ns
4
t
t(VCLK)
Transition time, VLYNQ_CLOCK
3
ns
Figure 7-80. VLYNQ_CLOCK Timing for VLYNQ
Table 7-98. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the
VLYNQ Module (see
-1G
NO
PARAMETER
FAST MODE
SLOW MODE
UNIT
.
MIN
MAX
MIN
MAX
t
d(VCLKH-
1
Delay time, VLYNQ_CLOCK high to VLYNQ_TXD[3:0] invalid
1
2.21
ns
TXDI)
t
d(VCLKH-
2
Delay time, VLYNQ_CLOCK high to VLYNQ_TXD[3:0] valid
7.14
8.5
ns
TXDV)
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
297
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