Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
VLYNQ_CLOCK
VLYNQ_TXD[3:0]
VLYNQ_RXD[3:0]
1
2
3
4
Data
Data
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-99. Timing Requirements for Receive Data for the VLYNQ Module
(1)
(see
-1G
NO.
UNIT
MIN
MAX
RTM disabled, RTM sample = 3
0.2
ns
Setup time, VLYNQ_RXD[3:0] valid before
3
t
su(RXDV-VCLKH)
VLYNQ_CLOCK high
RTM enabled
(1)
ns
RTM disabled, RTM sample = 3
2
ns
Hold time, VLYNQ_RXD[3:0] valid after
4
t
h(VCLKH-RXDV)
VLYNQ_CLOCK high
RTM enabled
(1)
ns
(1)
The VLYNQ receive timing manager (RTM) is a serial receive logic designed to eliminate setup and hold violations that could occur in
traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see
traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see
). When
RTM logic is disabled, the setup and hold timing from the default data flop (3) is used.
Table 7-100. RTM RX Data Flop Hold/Setup Timing
Constraints
RX Data Flop
HOLD (Y)
SETUP (X)
0
0.62
1.3
1
1.43
0.8
2
1.66
0.4
3
2.12
0.2
4
2.5
0
5
3.18
-0.3
6
3.87
-0.5
7
4.25
-0.7
Figure 7-81. VLYNQ Transmit/Receive Timing
298
Peripheral Information and Electrical Specifications
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